Patents by Inventor Arghya Sain
Arghya Sain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088047Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Sanka Ganesan, Robert L. Sankman, Arghya Sain, Sri Chaitra Jyotsna Chavali, Lijiang Wang, Cemil Geyik
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Patent number: 11869842Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.Type: GrantFiled: July 24, 2019Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Sanka Ganesan, Robert L. Sankman, Arghya Sain, Sri Chaitra Jyotsna Chavali, Lijiang Wang, Cemil Geyik
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Publication number: 20240006286Abstract: A substrate comprising a core structure between a first metallization stack and a second metallization stack. A hardware interface is at a side of the second metallization stack. A first interconnect comprises both a first via portion, and a first trace portion which extends from the first via portion in a first routing layer of the first metallization stack. The first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A second interconnect comprises both a second via portion, and a second trace portion which extends from the second via portion in the first routing layer. The second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A first multi-layer insulator structure adjoins respective sides of the first and second trace portions.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Arghya Sain, Sujit Sharan, Hoai V. Le, Jianyong Xie
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Publication number: 20230299044Abstract: In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Andrew P. Collins, Arghya Sain, Sujit Sharan, Jianyong Xie
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Patent number: 11705390Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.Type: GrantFiled: March 27, 2019Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Andrew Collins, Arghya Sain
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Publication number: 20230207405Abstract: Embodiments disclosed herein include electronic devices. In an embodiment, an electronic device comprises a core, where the core comprises a first layer comprising glass, and a second layer comprising glass over the first layer. In an embodiment, a trace is between the first layer and the second layer. In an embodiment, routing layers are on the core.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Arghya SAIN, Andrew P. COLLINS, Sivaseetharaman PANDI, Telesphor KAMGAING, Tolga ACIKALIN, Shuhei YAMADA
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Publication number: 20230207494Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a first layer that comprises glass. In an embodiment, a second layer comprising glass is over the first layer. In an embodiment, the electronic package further comprises an inductor between the first layer and the second layer.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Jianyong XIE, Andrew P. COLLINS, Arghya SAIN, Sivaseetharaman PANDI, Telesphor KAMGAING
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Publication number: 20230207406Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Arghya SAIN, Andrew P. COLLINS, Sivaseetharaman PANDI, Jianyong XIE, Telesphor KAMGAING
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Publication number: 20230197593Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass, and a first via through the core. In an embodiment, a first fin extends out laterally from the first via. In an embodiment, the electronic package further comprises a second via through the core, and a second fin extending out laterally from the second via. In an embodiment, a face of the first fin overlaps a face of the second fin.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Sivaseetharaman PANDI, Andrew P. COLLINS, Arghya SAIN, Telesphor KAMGAING
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Publication number: 20230197646Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Aleksandar ALEKSOV, Telesphor KAMGAING, Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Veronica STRONG, Brandon RAWLINGS, Andrew P. COLLINS, Arghya SAIN, Sivaseetharaman PANDI
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Publication number: 20230097236Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises: a core substrate. In an embodiment, the core substrate comprises glass. In an embodiment, a via passes through the core substrate. In an embodiment, a die is coupled to the package substrate, where the die comprises an IO interface. In an embodiment, the IO interface is electrically coupled to the via and the via is within a footprint of the die.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Andrew COLLINS, Aleksandar ALEKSOV, Srinivas V. PIETAMBARAM, Tarek A. IBRAHIM, Telesphor KAMGAING, Arghya SAIN, Sivaseetharaman PANDI
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Publication number: 20210296241Abstract: Embodiments may relate to a microelectronic package that includes an active die at a first side of the substrate and an interconnect at a second side of the substrate. A high-speed input/output (HSIO) die may also be coupled with the first side of substrate. The HSIO die may be coupled with the active die by a bridge. Other embodiments may be described or claimed.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Applicant: Intel CorporationInventors: Arghya Sain, Lesley A. Polka Wood, Russell K. Mortensen
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Publication number: 20210028116Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.Type: ApplicationFiled: July 24, 2019Publication date: January 28, 2021Inventors: Sanka GANESAN, Robert L. SANKMAN, Arghya SAIN, Sri Chaitra Jyotsna CHAVALI, Lijiang WANG, Cemil GEYIK
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Publication number: 20200343202Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.Type: ApplicationFiled: April 24, 2019Publication date: October 29, 2020Inventors: Lijiang WANG, Jianyong XIE, Arghya SAIN, Xiaohong JIANG, Sujit SHARAN, Kemal AYGUN
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Publication number: 20200312759Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: Andrew COLLINS, Arghya SAIN
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Patent number: 10475736Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.Type: GrantFiled: September 28, 2017Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch, Prashant D. Parmar, Sujit Sharan, Johanna M. Swan, Feras Eid
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Publication number: 20190096798Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: Intel CorporationInventors: Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch, Prashant D. Parmar, Sujit Sharan, Johanna M. Swan, Feras Eid