Abstract: A system includes converters, first modules, second modules, and a multiplexer. The converters receive an analog signal and a respective one of multiple clock signals. Each of the converters samples the analog signal based on a respective clock signal to generate a respective digital signal. Each of the clock signals is out-of-phase with other ones of the clock signals. The first modules receive the digital signals generated by the converters, remove bias offsets from the digital signals to generate first output signals, and output each of the first output signals on a multiple channels. The second modules receive the first output signals, and based on the first output signals, remove or equalize gain mismatch between the channels to generate second output signals. The multiplexer receives the second output signals, and generates an output based on the second output signals. The output is a digital representation of the analog signal.