Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components of the die to generate augmented versions of images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device. Other aspects relate to configuring under-the-array or next-to-the-array components of the die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of a NAND array to inject noise into the images.

Abstract: A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Abstract: Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

Abstract: The present disclosure generally relates to improving write cache utilization by recommending a time to initiate a data flush operation or predicting when a new write command will arrive. The recommending can be based upon considerations such as a hard time limit for data caching, rewarding for filling the cache, and penalizing for holding data for too long. The predicting can be based on tracking write command arrivals and then, based upon the tracking, predicting an estimated arrival time for the next write command. Based upon the recommendation or predicting, the write cache can be flushed or the data can remain in the write cache to thus more efficiently utilize the write cache without violating a hard stop time limit.

Abstract: Methods and apparatus are disclosed for managing the storage of static and dynamic neural network data within a non-volatile memory (NVM) die for use with deep neural networks (DNN). Some aspects relate to separate trim sets for separately configuring a static data NVM array for static input data and a dynamic data NVM array for dynamic synaptic weight data. For example, the static data NVM array may be configured via one trim set for data retention, whereas the dynamic data NVM array may be configured via another trim set for write performance. The trim sets may specify different configurations for error correction coding, write verification, and read threshold calibration, as well as different read/write voltage thresholds. In some examples, neural network regularization is provided within a DNN by setting trim parameters to encourage bit flips to avoid overfitting. Some examples relate to managing non-DNN data, such as stochastic gradient data.

Abstract: Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components of the die to generate augmented versions of images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device. Other aspects relate to configuring under-the-array or next-to-the-array components of the die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of a NAND array to inject noise into the images.

Abstract: The present disclosure generally relates to systems and methods by which a data storage device may receive data about the host system in which it is installed, and the customer associated with that system. Based upon this received data, the data storage device may modify its native operating parameters and custom functions to enable more optimal operation with the host system.

Abstract: Technology is disclosed for allocating PCIe bus bandwidth to storage commands in a peer-to-peer environment. A non-volatile storage system has a peer-to-peer connection with a host system and a target device, such as a GPU. A memory controller in the storage system monitors latency of PCIe transactions that are performed over a PCIe bus in order to transfer data for NVMe commands. The PCIe transactions may involve direct memory access (DMA) of memory in the host system or target device. There could be a significant difference in transaction latency depending on what memory is being accessed and/or what communication link is used to access the memory. The memory controller allocates bandwidth on a PCIe bus to the NVMe commands based on the latencies of the PCIe transactions. In an aspect, the memory controller groups the PCIe addresses based on the latencies of the PCIe transactions.

Abstract: A non-volatile storage system that is implementing a storage region (e.g., a persistent memory region) which is accessible to a host (e.g., via a PCIe connection) and a cache for the storage region shares details of the structure of the storage region and/or the cache (e.g., cache segment size). With awareness of the shared details of the structure of the storage region and/or the cache, the host arranges and sends out requests to read data from the persistent memory region in a manner that takes advantage of parallelism within the non-volatile storage system. For example, the host may initially send out one read request per cache segment to cause the non-volatile storage system to load the cache. Subsequently, additional read requests are made to the non-volatile storage system, with the data already loaded (or starting to load) in the cache, thereby increasing performance.

Abstract: A method and system for cache-based flow of a simple copy command is disclosed. The present disclosure generally relates to methods and systems for executing a simple copy command in a manner that mitigates additional latency in the device. According to certain embodiments, a copy command manager that includes one or more copy command slots is provided. When a simple copy command is received from a host, a copy command slot is allocated to the command, and the simple copy command is copied into the copy command slot. Upon copying the simple copy command to the copy command slot, an overlap table of the data storage device controller is updated to indicate the copy has been completed, and the completion is posted to the host. After posting, the simple copy command is carried out in the background through completion.

Abstract: A method and apparatus for enforcing privacy within one or more memories of a data storage system are disclosed. In one embodiment, sensor data containing personally identifiable information (PII) is provided to a memory. In some embodiments, the memory of disclosed systems and methods may be volatile, non-volatile, or a combination. Within the memory, PII is detected in some embodiments by AI-based computer vision, voice recognition, or natural language processing methods. Detected PII is obfuscated within the memory prior to making the sensor data available to other systems or memories. In some embodiments, once PII has been obfuscated, the original sensor data is overwritten, deleted, or otherwise made unavailable.

Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

Abstract: In the context of data storage, an approach to pre-fetching data prior to a read request involves receiving a read request and a next read request, and updating metadata corresponding to the read request with a next data storage address corresponding to the next read request. Responsive to again receiving the read request at a later time, the next data storage address can be read from the read request metadata and the next data can be pre-fetched from the next data storage address in advance of processing a following read request. Furthermore, the next data can be pre-fetched during read queue idle time and stored in a cache buffer, in anticipation of another incoming next read request, responsive to which the next data can be returned to the host from the buffer rather than from a read of non-volatile memory.

Abstract: A storage device includes a controller that can dynamically adjust the zone active limit (ZAL) for a zoned namespace (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjusted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjusted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. During a boot operation, the controller is configured to determine whether the boot is a device boot or a host boot. The controller includes a boot optimization unit. The boot optimization unit or the controller is configured to collect statistics of the fetched data, predict the data to be fetched next, and speculatively fetch the data. The controller further includes a rearrangement unit. The controller or the rearrangement unit is configured to rearrange data in the memory device based on the collect statistics of the fetched data so that the next boot operation is more optimized than the current boot operation.

Abstract: The present disclosure generally relate to dynamically changing predictive latency related attributes to increase the deterministic window (DTWIN) of operation. The host device workload characteristics as well as the memory device's current condition provide valuable information for the duration of the DTWIN. If the memory device is near the end of life, then the DTWIN duration will be smaller. Additionally, if the workload from the host device is heavy, then the DTWIN duration will also be smaller. Rather than utilizing a fixed DTWIN duration based upon worst case scenarios for host device workload and memory device condition, dynamically adjusting the DTWIN duration based upon the workload and condition will provide a DTWIN duration that can gradually decrease over time from a much longer DTWIN duration than is currently available.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. During a boot operation, the controller is configured to determine whether the boot is a device boot or a host boot. The controller includes a boot optimization unit. The boot optimization unit or the controller is configured to collect statistics of the fetched data, predict the data to be fetched next, and speculatively fetch the data. The controller further includes a rearrangement unit. The controller or the rearrangement unit is configured to rearrange data in the memory device based on the collect statistics of the fetched data so that the next boot operation is more optimized than the current boot operation.

Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives, and effective power management of the data storage device. The data storage device includes a controller, where the controller is configured to predict when a host device will send a command to enter a low power state, prepare the data storage device to enter the low power state, and receive a command to enter the low power state after the predicting and preparing. If the data storage device is idled for greater than a threshold value, then the data storage device prepares to transition to a low power state but will wait to enter the lower power state until receiving a request from a host device.