Patents by Inventor Ariel Shahar

Ariel Shahar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11323372
    Abstract: In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 3, 2022
    Assignee: MELLANOX TECHNOLOGIES LTD.
    Inventors: Avi Urman, Lior Narkis, Ariel Shahar
  • Publication number: 20220045844
    Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.
    Type: Application
    Filed: April 19, 2021
    Publication date: February 10, 2022
    Inventors: Miriam Menes, Noam Bloch, Adi Menachem, Idan Burstein, Ariel Shahar, Maxim Fudim
  • Publication number: 20220006606
    Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
    Type: Application
    Filed: June 1, 2021
    Publication date: January 6, 2022
    Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
  • Publication number: 20210406179
    Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
  • Publication number: 20210328923
    Abstract: In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 21, 2021
    Inventors: Avi Urman, Lior Narkis, Ariel Shahar
  • Publication number: 20210286646
    Abstract: A method using a memory and queue handling logic, including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Ariel Shahar, Roee Moyal
  • Patent number: 11102129
    Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 24, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Idan Burstein, Noam Bloch, Roee Moyal, Ariel Shahar, Yamin Friedman, Yuval Shpigelman
  • Patent number: 11055130
    Abstract: A method including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C. Related apparatus and methods are also provided.
    Type: Grant
    Filed: September 15, 2019
    Date of Patent: July 6, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ariel Shahar, Roee Moyal
  • Publication number: 20210111996
    Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.
    Type: Application
    Filed: December 1, 2020
    Publication date: April 15, 2021
    Inventors: Boris Pismenny, Miriam Menes, Idan Burstein, Liran Liss, Noam Bloch, Ariel Shahar
  • Publication number: 20210081207
    Abstract: A method including an executing entity, including fencing dependency circuitry, communicating with physical memory including a work queue (WQ) including a first controlling work request (WR), and a first dependent WR, the first dependent WR including a fencing indication indicating that the first dependent WR should not be executed until the first controlling WR has completed, the fencing dependency circuitry determining that the first dependent WR is ready for execution and checking, based on the fencing indication in the first dependent WR, whether the first controlling WR has completed, and the executing entity executing the first dependent WR only when the first controlling WR has completed. Related apparatus and methods are also provided.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Ariel Shahar, Ahmad Omary
  • Publication number: 20210081236
    Abstract: A method including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C. Related apparatus and methods are also provided.
    Type: Application
    Filed: September 15, 2019
    Publication date: March 18, 2021
    Inventors: Ariel Shahar, Roee Moyal
  • Patent number: 10852967
    Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: December 1, 2020
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Ariel Shahar, Peter Paneah, Maxim Zaborov
  • Patent number: 10824469
    Abstract: A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 3, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Eitan Hirshberg, Ariel Shahar, Najeeb Darawshy, Omri Kahalon
  • Patent number: 10757183
    Abstract: A method for communication includes receiving in a computer system a request from a peer computer system. Upon finding that the computer system is currently not ready to process the request, a Negative Acknowledgement (NAK) message is sent from the computer system to the peer computer system, at a sending time that is derived from a time at which the computer system is ready to process the request.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 25, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ariel Shahar, Shahaf Shuler, Lion Levi
  • Publication number: 20200167192
    Abstract: A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Eitan Hirshberg, Ariel Shahar, Najeeb Darawshy, Omri Kahalon
  • Patent number: 10642775
    Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: May 5, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Igor Voks, Dror Bohrer, Lior Narkis, Ariel Shahar
  • Publication number: 20200084150
    Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 12, 2020
    Inventors: Idan Burstein, Noam Bloch, Roee Moyal, Ariel Shahar, Yamin Friedman, Yuval Shpigelman
  • Patent number: 10505677
    Abstract: A network element processes a data flow in accordance with a communications protocol in which respective incremental sequence numbers are assigned to segments of the data flow. The segments are sent from the network element to the other network element in order of the sequence numbers, and respective acknowledgements are received from the other network element. The acknowledgements may include the highest sequence number of the segments of the flow that were received in the other network element. After transmitting the last segment of the data flow an additional segment is sent to the other network element. When it is determined from an acknowledgement of the additional segment that the last segment of the data flow was not received by the other network element, the last segment is retransmitted.
    Type: Grant
    Filed: October 29, 2017
    Date of Patent: December 10, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Alexander Shpiner, Adi Menachem, Eitan Zahavi, Noam Bloch, Ariel Shahar
  • Publication number: 20190332291
    Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.
    Type: Application
    Filed: April 26, 2018
    Publication date: October 31, 2019
    Inventors: Ariel Shahar, Peter Paneah, Maxim ZABOROV
  • Patent number: 10462060
    Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 29, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Jacob Ruthstein, David Mozes, Dror Bohrer, Ariel Shahar, Lior Narkis, Noam Bloch