Abstract: A MEMS device chip manufacturing method including a grinding step of grinding a device forming area of a wafer to thereby form a recess and an annular reinforcing portion surrounding the recess, a MEMS device forming step of performing any processing including etching to the wafer after performing the grinding step to thereby form a plurality of MEMS devices partitioned by a plurality of crossing division lines in the device forming area, and a dividing step of dividing the wafer along the division lines after performing the MEMS device forming step to thereby manufacture a plurality of MEMS device chips.

Abstract: A MEMS device chip manufacturing method including a grinding step of grinding a device forming area of a wafer to thereby form a recess and an annular reinforcing portion surrounding the recess, a MEMS device forming step of performing any processing including etching to the wafer after performing the grinding step to thereby form a plurality of MEMS devices partitioned by a plurality of crossing division lines in the device forming area, and a dividing step of dividing the wafer along the division lines after performing the MEMS device forming step to thereby manufacture a plurality of MEMS device chips.

Abstract: A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A method for fabricating a composite interposer comprising disposing a silicon layer on a substrate, and selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate. Vias are formed through the exposed part of the substrate. The method additionally includes filling the vias and the silicon openings with a filler material (e.g.

Abstract: A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A method for fabricating a composite interposer comprising disposing a silicon layer on a substrate, and selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate. Vias are formed through the exposed part of the substrate. The method additionally includes filling the vias and the silicon openings with a filler material (e.g.