Abstract: An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

Abstract: An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

Abstract: A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reducing routing signals. An apparatus includes a first block decoder circuit that senses bad block data of a first latch circuit corresponding to a first memory block and couple the bad block data onto a bus. An apparatus includes a comparator circuit that compares the bad block data against a reference, sets a bad block flag, and routes the bad block flag on a routing line across an array of storage elements. An apparatus includes a second block decoder circuit that receives the bad block flag from the routing line, determines a condition of the first memory block based on the bad block flag, and determines a generation of a block selection signal for selecting a second memory block.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

Abstract: A method includes receiving, from a client enterprise, at a provider computing device, a request for price quote for products provided by a provider enterprise and determining a plurality of discrete processing units based on the request for price quote. The method includes assigning each of the plurality of discrete processing units to a single one of a plurality of parallel processing devices. The method includes accessing, by each of the plurality of parallel processing devices, price quote generation data stored in a hierarchical manner in a database associated with the provider, and processing the discrete processing units the plurality of discrete processing units based on the price quote generation data to generate a corresponding plurality of processed units. The method includes merging the processed units to form concatenated processed units and adding global components to the concatenated processed units to form the price quote.