Abstract: An in-vivo devices (600) includes a combined sensor array (600) having a first sensor array sensitive to a first wavelength range and a second sensor array sensitive to a second wavelength range, where the second wavelength has a partial overlap with the first wavelength range, the first sensor array is configured for collecting light in the first wavelength range and outputting a corresponding first signal, and the second sensor array is configured for collecting light in the second wavelength range and outputting a corresponding second signal. The in-vivo device further includes a processor (630) configured for receiving the first signal and the second signal, manipulating the first signal based on at least a part of the second signal corresponding to the partial overlap to output a first image, and outputting a second image based on the second signal.

Abstract: A system for diagnosing an esophageal disease includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the system to: access, during a procedure involving an in-vivo device located within a person, data measured by the in-vivo device relating to an esophageal disease; evaluate, during the procedure while the in-vivo device is located within the person, a diagnosis for the esophageal disease for the person by applying a trained machine learning model to the data measured by the in-vivo device; and communicate, during the procedure while the in-vivo device is located within the person, the diagnosis for the esophageal disease.

Abstract: An on/off switching circuit includes an on/off switch switchable between an on state and an off state, an light emitting diode (LED) driver to power one or more LEDs to illuminate an area of interest, a switch control unit to transition the on/off switch between the on and off states, the switch control unit including a light sensing circuit comprising at least one LED of the LEDs as a light sensor, and a bi-directional gate circuit. When the on/off switch is in the off state the bi-directional gate is in a first conducting state in which the bi-directional gate circuit connects the light sensor to the light sensing circuit, and when the on/off switch is in the on state the bi-directional gate is in a second conducting state in which the bi-directional gate connects the LED driver to the one or more LEDs including the light sensor.

Abstract: An on/off switching circuit includes an on/off switch switchable between an on state and an off state, an light emitting diode (LED) driver to power one or more LEDs to illuminate an area of interest, a switch control unit to transition the on/off switch between the on and off states, the switch control unit including a light sensing circuit comprising at least one LED of the LEDs as a light sensor, and a bi-directional gate circuit. When the on/off switch is in the off state the bi-directional gate is in a first conducting state in which the bi-directional gate circuit connects the light sensor to the light sensing circuit, and when the on/off switch is in the on state the bi-directional gate is in a second conducting state in which the bi-directional gate connects the LED driver to the one or more LEDs including the light sensor.

Abstract: A computer program product for provision of prioritization metrics for post-Si failure localization is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to, receive an output of a failure localization tool applied to hardware verification debug processing, recognize, from the output, numbers of mis-compared resources to which each instruction of the failure localization tool is related, apply a priority gradient to each instruction based on the corresponding numbers of the mis-compared resources and conduct further debug processing with respect to each instruction in accordance with the applied priority gradient.

Abstract: A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal.

Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.

Abstract: A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.

Abstract: An ion concentration sensor produces a signal reflective of the ion concentration within a solution. The ion concentration sensor is based on an ion sensitive transistor having a solution input, a reference input, a diffusion input, and a diffusion output. The ion sensitive transistor is connected as a pass transistor, such that the diffusion output provides an electrical signal indicating an ion concentration in a solution contacting the solution input.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.

Abstract: A method of designing logic circuit provides a logic circuit which includes a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. The third transistor network has a complementary structure to the transistors between the intermediate node and the central node, and includes a logic output The third transistor network (the graft network) provides a second logic output to the logic circuit.

Abstract: An ion concentration sensor produces a signal reflective of the ion concentration within a solution. The ion concentration sensor is based on an ion sensitive transistor having a solution input, a reference input, a diffusion input, and a diffusion output. The ion sensitive transistor is connected as a pass transistor, such that the diffusion output provides an electrical signal indicating an ion concentration in a solution contacting the solution input.

Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Abstract: An ion concentration sensor produces a signal reflective of the ion concentration within a solution. The ion concentration sensor is based on an ion sensitive transistor having a solution input, a reference input, a diffusion input, and a diffusion output. The ion sensitive transistor is connected as a pass transistor, such that the diffusion output provides an electrical signal indicating an ion concentration in a solution contacting the solution input.