Abstract: A receiver of signals modulated by pseudorandom noise that uses a hierarchy of delay lock loops (DLLs) to maintain code lock. Each DLL in the hierarchy produces a control signal representative of a timing mismatch between the incoming signal and an internally generated pseudorandom noise code, preferably by correlating the incoming signal with early and late instances of the code and subtracting the late correlation from the early correlation. The early correlation is advanced relative to the late correlation by successively shorter spacings in successively lower DLLs in the hierarchy. In each DLL, the control signal is transformed to a code phase signal for adjusting the timing of the code generator. In the lower DLLs, this code phase signal is compared to the delay signal of the immediately higher DLL and adjusted accordingly.

Abstract: A method of chip interleaving in direct sequence spread spectrum communications. A binary code sequence is chosen to have a length N=2k−1 and to be self-orthogonal. A data string of M=QN+1 bits, QN−1 bits, or QN+S bits, where Q is a positive integer and S is an integer between 1 and N that lacks a common factor with N, is multiplied sequentially with the binary code sequence until N chip frames of M chips each are produced. These chip frames are transmitted to a receiver, and recovered in an equally straightforward manner. The integers Q and N are chosen according to transmission conditions.

Abstract: A receiver of signals modulated by pseudorandom noise that uses a hierarchy of delay lock loops (DLLs) to maintain code lock. Each DLL in the hierarchy produces a control signal represenative of a timing mismatch between the incoming signal and an internally generated pseudorandom noise code, preferably by correlating the incoming signal with early and late instances of the code and subtracting the late correlation from the early correlation. The early correlation is advanced relative to the late correlation by successively shorter spacings in successively lower DLLs in the hierarchy. In each DLL, the control signal is transformed to a code phase signal for adjusting the timing of the code generator. In the lower DLLs, this code phase signal is compared to the delay signal of the immediately higher DLL and adjusted accordingly.

Abstract: A method of chip interleaving in direct sequence spread spectrum communications. A binary code sequence is chosen to have a length N=2.sup.k -1 and to be self-orthogonal. A data string of M=QN.+-.1 bits, where Q is a positive integer, is multiplied sequentially with the binary code sequence until N chip frames of M chips each are produced. These chip frames are transmitted to a receiver, and recovered in an equally straightforward manner. The integers Q and N are chosen according to transmission conditions.