Abstract: A fuze having an impact delay implemented by strobing the count from a time-of-flight counter to set a down counter after an impact is sensed and then decrementing the down counter to a predetermined count at which point a firing signal is passed.

Abstract: A power-on reset circuit in which a first CMOS inverter drives a second CMOS inverter to turn on a third and fourth CMOS inverter. A reset pulse results at the output of the fourth inverter while the third inverter holds a first MOSFET in an off condition and a capacitor is charged through a resistive network comprised of two MOSFETs. When the capacitor is charged past the switching point of the first inverter, the POR pulse is terminated and the first MOSFET is turned on, allowing the capacitor to be charged to the point that no static current flows through the reset circuit because no static current flows through the first inverter.