Patents by Inventor Armand Pruijmboom
Armand Pruijmboom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220376479Abstract: A semiconductor device comprising an array of vertical cavity surface emitting lasers (VCSELs). The semiconductor device includes a first VCSEL having a first active area, a second VCSEL having a second active area, and a bridge connecting the first VCSEL and the second VCSEL. The first active area of the first VCSEL and the second active area of the second VCSEL are arranged along a first crystal axis. The semiconductor device further includes a blocking structure arranged between the first VCSEL and the second VCSEL. the blocking structure is configured to block a propagation of a defect between the first VCSEL and the second VCSEL along the first crystal axis.Type: ApplicationFiled: May 11, 2022Publication date: November 24, 2022Inventors: Alexander Weigl, Armand Pruijmboom
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Patent number: 9573385Abstract: The invention relates to a laser based printing apparatus (100) using laser light sources (111, 112, 113, 402, 404, 406, 604, 606, 808, 810) for supplying energy to a target object (120) to form an image.Type: GrantFiled: March 16, 2011Date of Patent: February 21, 2017Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Holger Moench, Stephan Gronenborn, Armand Pruijmboom
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Patent number: 9172213Abstract: The invention describes a method of manufacturing a VCSEL module (100) comprising at least one VCSEL chip (33) with an upper side (U) and a lower side (L) and with a plurality of VCSEL units (55) on a common carrier structure (35), the VCSEL units (55) comprising a first doped layer (50) of a first type facing towards the lower side (L) and a second doped layer (23) of a second type facing towards the upper side (U). The method comprises the steps of dividing the VCSEL chip (33) into a plurality of subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) with at least one VCSEL unit (55) each, electrically connecting at least some of the subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) in series. The invention also describes a VCSEL module (100) manufactured in such process.Type: GrantFiled: February 22, 2013Date of Patent: October 27, 2015Assignee: Koninklijke Philips N.V.Inventors: Stephan Gronenborn, Armand Pruijmboom, Raimond Louis Dumoulin, Michael Miller
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Patent number: 9091747Abstract: The proposed self-mixing interference device comprises a substrate (1) with an integrated optical wave guide structure (3), a semiconductor laser source (2) arranged on a surface of the substrate (1) and emitting laser radiation towards said surface, and a photodetector arranged to detect intensity variations of the laser radiation. The wave guide structure (3) is optically connected to the laser source (2) and designed to guide the laser radiation emitted by the laser source to an out-coupling area at the surface of the substrate (1) and to guide a portion of the laser radiation scattered back from a target object (4) outside of the substrate (1) to re-enter the laser source (2). This self-mixing interference device can be realized with a lower total height compared to the known self-mixing interference devices.Type: GrantFiled: October 18, 2010Date of Patent: July 28, 2015Assignee: KONINKLIJKE PHILIPS N.V.Inventor: Armand Pruijmboom
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Patent number: 9065235Abstract: The present invention relates to a method of assembling VCSEL chips (1) on a sub-mount (2). A de-wetting layer (13) is deposited on a connecting side of the VCSEL chips (1) which is to be connected to the sub-mount (2). A further de-wetting layer (13) is deposited on a connecting side of the sub-mount (2) which is to be connected to the VCSEL chips (1). The de-wetting layers (13) are deposited with a patterned design or are patterned after depositing to define connecting areas (21) on the sub-mount (2) and the VCSEL chips (1). A solder (15) is applied to the connecting areas (21) of at least one of the two connecting sides. The VCSEL chips (1) are placed on the sub-mount (2) and soldered to the sub-mount (2) to electrically and mechanically connect the VCSEL chips (1) and the sub-mount (2). With the proposed method a high alignment accuracy of the VCSEL chips (1) on the sub-mount (2) is achieved without time consuming measures.Type: GrantFiled: October 8, 2012Date of Patent: June 23, 2015Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Armand Pruijmboom, Raimond Louis Dumoulin, Michael Miller
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Publication number: 20150071320Abstract: The invention describes a method of manufacturing a VCSEL module (100) comprising at least one VCSEL chip (33) with an upper side (U) and a lower side (L) and with a plurality of VCSEL units (55) on a common carrier structure (35), the VCSEL units (55) comprising a first doped layer (50) of a first type facing towards the lower side (L) and a second doped layer (23) of a second type facing towards the upper side (U). The method comprises the steps of dividing the VCSEL chip (33) into a plurality of subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) with at least one VCSEL unit (55) each, electrically connecting at least some of the subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) in series. The invention also describes a VCSEL module (100) manufactured in such process.Type: ApplicationFiled: February 22, 2013Publication date: March 12, 2015Inventors: Stephan Gronenborn, Armand Pruijmboom, Raimond Louis Dumoulin, Michael Miller
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Publication number: 20140348192Abstract: The present invention relates to a method of assembling VCSEL chips (1) on a sub-mount (2). A de-wetting layer (13) is deposited on a connecting side of the VCSEL chips (1) which is to be connected to the sub-mount (2). A further de-wetting layer (13) is deposited on a connecting side of the sub-mount (2) which is to be connected to the VCSEL chips (1). The de-wetting layers (13) are deposited with a patterned design or are patterned after depositing to define connecting areas (21) on the sub-mount (2) and the VCSEL chips (1). A solder (15) is applied to the connecting areas (21) of at least one of the two connecting sides. The VCSEL chips (1) are placed on the sub-mount (2) and soldered to the sub-mount (2) to electrically and mechanically connect the VCSEL chips (1) and the sub-mount (2). With the proposed method a high alignment accuracy of the VCSEL chips (1) on the sub-mount (2) is achieved without time consuming measures.Type: ApplicationFiled: October 8, 2012Publication date: November 27, 2014Inventors: Armand Pruijmboom, Raimond Louis Dumoulin, Michael Miller
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Publication number: 20130176375Abstract: The invention relates to a laser based printing apparatus (100) using laser light sources (111, 112, 113, 402, 404, 406, 604, 606, 808, 810) for supplying energy to a target object (120) to form an image.Type: ApplicationFiled: March 16, 2011Publication date: July 11, 2013Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Holger Moench, Stephan Gronenborn, Armand Pruijmboom
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Patent number: 8378287Abstract: The invention relates to an optical sensor module (1) for a measuring device. Said module comprises at least one optical sensor (2) including a diode laser (3) having a laser cavity for generating a measuring beam, the diode laser being attached to a substrate (12), converging means (5) (such as a lens). During measuring, such converging means (5) converges the measuring beam in an action plane and converges in the laser cavity the measuring beam radiation that has been back-scattered by an object to generate a self-mixing effect and means for measuring the self-mixing effect. Later means comprise a photo diode (4) and an associated signal processing circuitry. According to an essential aspect of the invention, that the diode laser (3) is configured to emit laser radiation of a wavelength for which the substrate (12) being attached to the diode laser (3) is transparent. This configuration leads to an essentially simple (and therefore cheap) sensor module.Type: GrantFiled: June 23, 2008Date of Patent: February 19, 2013Assignee: Koninklijke Philips Electronics N.V.Inventors: Marcel Franz Christian Schemmann, Armand Pruijmboom, Silvia Maria Booij, Klaus Peter Werner
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Publication number: 20120200858Abstract: The proposed self-mixing interference device comprises a substrate (1) with an integrated optical wave guide structure (3), a semiconductor laser source (2) arranged on a surface of the substrate (1) and emitting laser radiation towards said surface, and a photodetector arranged to detect intensity variations of the laser radiation. The wave guide structure (3) is optically connected to the laser source (2) and designed to guide the laser radiation emitted by the laser source to an out-coupling area at the surface of the substrate (1) and to guide a portion of the laser radiation scattered back from a target object (4) outside of the substrate (1) to re-enter the laser source (2). This self-mixing interference device can be realized with a lower total height compared to the known self-mixing interference devices.Type: ApplicationFiled: October 18, 2010Publication date: August 9, 2012Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventor: Armand Pruijmboom
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Publication number: 20100187449Abstract: The invention relates to an optical sensor module (1) for a measuring device. Said module comprises at least one optical sensor (2) including a diode laser (3) having a laser cavity for generating a measuring beam, the diode laser being attached to a substrate (12), converging means (5) (such as a lens). During measuring, such converging means (5) converges the measuring beam in an action plane and converges in the laser cavity the measuring beam radiation that has been back-scattered by an object to generate a self-mixing effect and means for measuring the self-mixing effect. Later means comprise a photo diode (4) and an associated signal processing circuitry. According to an essential aspect of the invention, that the diode laser (3) is configured to emit laser radiation of a wavelength for which the substrate (12) being attached to the diode laser (3) is transparent. This configuration leads to an essentially simple (and therefore cheap) sensor module.Type: ApplicationFiled: June 23, 2008Publication date: July 29, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Marcel Franz Christian Schemmann, Armand Pruijmboom, Silvia Maria Booij, Klaus Peter Werner
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Patent number: 6611044Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.Type: GrantFiled: August 26, 1999Date of Patent: August 26, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Armand Pruijmboom, David M. Szmyd, Reinhard Germany Brock
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Publication number: 20020030244Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.Type: ApplicationFiled: August 26, 1999Publication date: March 14, 2002Inventors: ARMAND PRUIJMBOOM, DAVID M. SZMYD, REINHARD BROCK
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Patent number: 5970332Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is destined for the bipolar transistor and a second region (7) for the MOS transistor. The second region is provided with a gate dielectric (10). Then an electrode layer of non-crystalline silicon (11) is provided on the surface, which electrode layer is provided with a doping and in which electrode layer subsequently an emitter electrode (12) is formed on the first region and a gate electrode (13) on the second region.Type: GrantFiled: March 27, 1996Date of Patent: October 19, 1999Assignee: U.S. Philips CorporationInventors: Armand Pruijmboom, Alexander C. L. Jansen, Ronald Koster, Willem Van Der Wel
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Patent number: 5895248Abstract: A method of a manufacturing a semiconductor device whereby a layer of insulating material and a layer of polycrystalline silicon are provided on a surface of a monocrystalline wafer. A window is then provided in the layer of polycrystalline silicon and a protective layer is formed on the wall of this window. Then the layer of insulating material is removed within the window and below an edge of the layer of polycrystalline silicon adjoining the window. Subsequently, silicon is selectively grown on the mono- and polycrystalline silicon exposed in and adjacent the window from a vapor comprising chlorine as well as silicon at low pressure. The silicon wafer is cleaned before the selective deposition through heating in an atmosphere comprising hydrogen at a pressure of at least 1 atmosphere. This cleaning safeguards that the deposited monocrystalline silicon will always be connected to the layer of polycrystalline silicon by the deposited polycrystalline silicon.Type: GrantFiled: October 21, 1996Date of Patent: April 20, 1999Assignee: U.S. Philips CorporationInventors: Wiebe B. De Boer, Matthias J.J. Theunissen, Armand Pruijmboom
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Patent number: 5824560Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region.Type: GrantFiled: March 27, 1996Date of Patent: October 20, 1998Assignee: U.S. Philips CorporationInventors: Willem Van Der Wel, Alexander C. L. Jansen, Ronald Koster, Armand Pruijmboom
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Patent number: 5629554Abstract: A semiconductor device with a bipolar transistor formed in a layer of semiconductor material (2) provided on an insulating substrate (1), in which material a collector zone (4), a base zone (5), and an emitter zone (6) are provided below a strip of insulating material (3) situated on the layer (2), which zones are connected to contact regions (7, 8, 9, 10) lying adjacent the strip (3), three of the contact regions (8, 9, 10) lying next to one another at a same side of the strip (3), of which two (8 and 9) are connected to the base zone (5) while the third (10), which lies between the former two (8 and 9), is connected to the emitter zone (6). The three contact regions (8, 9, 10) situated next to another at the same side of the strip (3) are provided alternately in the layer of semiconductor material (2) and in a further layer of semiconductor material (19) extending up to the strip (3).Type: GrantFiled: April 24, 1996Date of Patent: May 13, 1997Assignee: U.S. Philips CorporationInventors: Henricus G. R. Maas, Ronald Dekker, Armand Pruijmboom
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Patent number: 5554256Abstract: A method of manufacturing a semiconductor device comprising a semiconductor body (1) with field insulation regions (14) formed by grooves (10; 24) filled with an insulating material (13) is disclosed. The grooves (10; 24) are etched into the semiconductor body (1) with the use of an etching mask (9) formed on an auxiliary layer (6) provided on a surface (5) of the semiconductor body (1). The auxiliary layer (6) is removed from the portion (11) of the surface (5) situated next to the etching mask (9) before the grooves (10; 24) are etched into the semiconductor body (1), and the auxiliary layer (6) is removed from the edge (12) of the surface (5) situated below the etching mask (9) after the grooves (10; 24) have been etched into the semiconductor body. Furthermore, a layer (13) of the insulating material is deposited on the semiconductor body (1), whereby the grooves (10; 24) are filled and the edge (12) of the surface (5) situated below the etching mask (9) is covered.Type: GrantFiled: September 22, 1994Date of Patent: September 10, 1996Assignee: U.S. Philips CorporationInventors: Armand Pruijmboom, Ronald Koster, Cornelis E. Timmering, Ronald Dekker
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Patent number: 5405789Abstract: A method of manufacturing a semiconductor device with a semiconductor element which includes a semiconductor zone (19) situated below an electrode (18) and adjoining a surface (5) of a semiconductor body (1), which semiconductor zone substantially does not project outside the electrode (18) in lateral direction. The electrode (18) is here formed on the surface (5) of the semiconductor body (1), after which semiconductor material adjoining the surface (5) and not covered by the electrode (18) is removed by an etching treatment, whereby the position of the semiconductor zone (19) below the electrode (18) is defined.Type: GrantFiled: October 22, 1993Date of Patent: April 11, 1995Assignee: U.S. Philips CorporationInventors: Ronald Dekker, Henricus G. R. Maas, Armand Pruijmboom, Wilhelmus T. A. J. Van Den Einden
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Patent number: 5268313Abstract: A method of manufacturing a semiconductor device whereby an spacer is formed from a second layer in a fully self-registering manner after a layer portion of a first layer has been formed. For this purpose, the second layer and a masking layer are provided in that order, which masking layer has a greater thickness next to the layer portion than above it. The portion of the second layer situated above the layer portion and the spacer to be formed is then exposed in that the masking layer is etched back over at least substantially its entire surface. A portion of the masking layer then remains next to the layer portion, which masking layer portion is sufficiently thick for adequately protecting the subjacent portion of the second layer against the treatment which is subsequently carried out and by which the etching resistance of at least the top layer of the exposed portion of the second layer is increased.Type: GrantFiled: January 13, 1992Date of Patent: December 7, 1993Assignee: U.S. Philips CorporationInventors: Henricus G. R. Maas, Armand Pruijmboom, Peter H. Kranen, Johanna M. L. Van Rooij-Mulder, Marguerite M. C. Van Iersel-Schiffmacher