Patents by Inventor Armando Tresvalles Clarina, JR.

Armando Tresvalles Clarina, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS
    Publication number: 20210375808
    Abstract: In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 2, 2021
    Inventors: Arvin Cedric Quiambao Mallari, Maricel Fabia Escano, Armando Tresvalles Clarina, JR., Jovenic Romero Esquejo
  • Packaged semiconductor device with electroplated pillars
    Patent number: 11094656
    Abstract: In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arvin Cedric Quiambao Mallari, Maricel Fabia Escano, Armando Tresvalles Clarina, Jr., Jovenic Romero Esquejo
  • Semiconductor package having a metal barrier
    Patent number: 10797010
    Abstract: A semiconductor device having a barrier metal layer positioned over a metallization layer, and an under bump metallurgy layer over the barrier metal layer, and a solder bump over the under bump metallurgy layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 6, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joel Tomas Medina, Armando Tresvalles Clarina, Jr., Jay-Ar Tumaru Flores, Ruby Ann Dizon Mamangun
  • PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS
    Publication number: 20200211990
    Abstract: In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.
    Type: Application
    Filed: February 1, 2019
    Publication date: July 2, 2020
    Inventors: Arvin Cedric Quiambao Mallari, Maricel Fabia Escano, Armando Tresvalles Clarina, JR., Jovenic Romero Esquejo
  • SEMICONDUCTOR PACKAGE HAVING A METAL BARRIER
    Publication number: 20190206817
    Abstract: A semiconductor device having a barrier metal layer positioned over a metallization layer, and an under bump metallurgy layer over the barrier metal layer, and a solder bump over the under bump metallurgy layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Joel Tomas MEDINA, Armando Tresvalles CLARINA, JR., Jay-Ar Tumaru FLORES, Ruby Ann Dizon MAMANGUN
  • Semiconductor devices having metal bumps with flange
    Patent number: 9564410
    Abstract: A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: February 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Floro Lopez Camenforte, III, James Raymond Maliclic Baello, Armando Tresvalles Clarina, Jr.
  • SEMICONDUCTOR DEVICES HAVING METAL BUMPS WITH FLANGE
    Publication number: 20170012012
    Abstract: A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.
    Type: Application
    Filed: July 8, 2015
    Publication date: January 12, 2017
    Inventors: Floro Lopez Camenforte, III, James Raymond Maliclic Baello, Armando Tresvalles Clarina, JR.