Abstract: The implementation of two-dimensional decoding, necessary to achieve a reasonable array aspect ratio for a large content addressable memory, is achieved by having multiple match lines per physical row, these match lines being physically routed on top of the array core cell in an upper metal layer. To limit power dissipation in the resulting large-capacity content addressable memory, the match function is implemented by two or more NAND chains per word. Means for achieving the precharging and evaluation of these chains, and for implementing dummy chains for the provision of timing information, are also disclosed.