Patents by Inventor Armin HAJ ABOUTALEBI

Armin HAJ ABOUTALEBI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11899589
    Abstract: A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: February 13, 2024
    Inventors: Armin Haj Aboutalebi, Rekha Pitchumani, Zongwang Li, Marie Mai Nguyen
  • Patent number: 11791838
    Abstract: An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 17, 2023
    Inventors: Sahand Salamat, Joo Hwan Lee, Armin Haj Aboutalebi, Praveen Krishnamoorthy, Xiaodong Zhao, Hui Zhang, Yang Seok Ki
  • Patent number: 11567971
    Abstract: A method of processing data in a system having a host and a storage node may include performing a shuffle operation on data stored at the storage node, wherein the shuffle operation may include performing a shuffle write operation, and performing a shuffle read operation, wherein at least a portion of the shuffle operation is performed by an accelerator at the storage node. A method for partitioning data may include sampling, at a device, data from one or more partitions based on a number of samples, transferring the sampled data from the device to a host, determining, at the host, one or more splitters based on the sampled data, communicating the one or more splitters from the host to the device, and partitioning, at the device, data for the one or more partitions based on the one or more splitters.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 31, 2023
    Inventors: Hui Zhang, Joo Hwan Lee, Yiqun Zhang, Armin Haj Aboutalebi, Xiaodong Zhao, Praveen Krishnamoorthy, Andrew Chang, Yang Seok Ki
  • Publication number: 20220405207
    Abstract: A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.
    Type: Application
    Filed: October 13, 2021
    Publication date: December 22, 2022
    Inventors: Armin HAJ ABOUTALEBI, Rekha PITCHUMANI, Zongwang LI, Marie Mai NGUYEN
  • Publication number: 20220231698
    Abstract: An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.
    Type: Application
    Filed: June 24, 2021
    Publication date: July 21, 2022
    Inventors: Sahand SALAMAT, JOO HWAN LEE, ARMIN HAJ ABOUTALEBI, PRAVEEN KRISHNAMOORTHY, XIAODONG ZHAO, HUI ZHANG, YANG SEOK KI
  • Publication number: 20220156287
    Abstract: A method of processing data in a system having a host and a storage node may include performing a shuffle operation on data stored at the storage node, wherein the shuffle operation may include performing a shuffle write operation, and performing a shuffle read operation, wherein at least a portion of the shuffle operation is performed by an accelerator at the storage node. A method for partitioning data may include sampling, at a device, data from one or more partitions based on a number of samples, transferring the sampled data from the device to a host, determining, at the host, one or more splitters based on the sampled data, communicating the one or more splitters from the host to the device, and partitioning, at the device, data for the one or more partitions based on the one or more splitters.
    Type: Application
    Filed: December 4, 2020
    Publication date: May 19, 2022
    Inventors: HUI ZHANG, JOO HWAN LEE, YIQUN ZHANG, ARMIN HAJ ABOUTALEBI, XIAODONG ZHAO, PRAVEEN KRISHNAMOORTHY, ANDREW CHANG, YANG SEOK KI
  • Publication number: 20220107844
    Abstract: A method of partitioning a graph for processing may include sorting two or more vertices of the graph based on incoming edges and outgoing edges, placing a first one of the vertices with fewer incoming edges in a first partition, and placing a second one of the vertices with fewer outgoing edges in a second partition. The first one of the vertices may have a lowest number of incoming edges, and the first one of the vertices may be placed in a first available partition. The second one of the vertices may have a lowest number of outgoing edges, and the second one of the vertices may be placed in a second available partition. A method for updating vertices of a graph may include storing a first update in a first buffer, storing a second update in a second buffer, and transferring the first and second updates to a memory using different threads.
    Type: Application
    Filed: February 8, 2021
    Publication date: April 7, 2022
    Inventors: Soheil KHADIRSHARBIYANI, Nima ELYASI, Armin HAJ ABOUTALEBI, Changho CHOI