Patents by Inventor Armin Stingl
Armin Stingl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012727Abstract: A processor includes execution circuitry, within an execution power domain, to process an instruction; and a debug system, within a separate debug power domain, to selectively operate to perform debugging operations on the processor. The processor further includes power control circuitry coupled to the debug system; and detection circuitry coupled to the power control circuitry. The power control circuitry causes power to be supplied to the debug system when the detection circuitry indicates that a debug tool is coupled to the processor, and disables power supply to the debug system when the detection circuitry indicates that the debug tool is not coupled to the processor.Type: ApplicationFiled: September 26, 2023Publication date: January 11, 2024Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Patent number: 11868780Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.Type: GrantFiled: August 26, 2021Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christian Wiencke, Armin Stingl, Jeroen Vliegen
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Patent number: 11803455Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: GrantFiled: February 28, 2023Date of Patent: October 31, 2023Assignee: Texas Instruments IncorporatedInventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Publication number: 20230205656Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: ApplicationFiled: February 28, 2023Publication date: June 29, 2023Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Patent number: 11593241Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: GrantFiled: January 12, 2021Date of Patent: February 28, 2023Assignee: Texas Instmments IncorporatedInventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Publication number: 20210382721Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.Type: ApplicationFiled: August 26, 2021Publication date: December 9, 2021Inventors: Christian Wiencke, Armin Stingl, Jeroen Vliegen
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Patent number: 11132203Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.Type: GrantFiled: August 14, 2014Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christian Wiencke, Armin Stingl, Jeroen Vliegen
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Publication number: 20210133065Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: ApplicationFiled: January 12, 2021Publication date: May 6, 2021Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Patent number: 10929101Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.Type: GrantFiled: August 6, 2018Date of Patent: February 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christian Wiencke, Armin Stingl
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Patent number: 10891207Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: GrantFiled: August 13, 2018Date of Patent: January 12, 2021Assignee: Texas Instruments IncorporatedInventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Publication number: 20180349097Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.Type: ApplicationFiled: August 6, 2018Publication date: December 6, 2018Inventors: Christian Wiencke, Armin Stingl
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Publication number: 20180349241Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: ApplicationFiled: August 13, 2018Publication date: December 6, 2018Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Patent number: 10049025Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: GrantFiled: July 1, 2016Date of Patent: August 14, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Patent number: 10042605Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.Type: GrantFiled: April 19, 2016Date of Patent: August 7, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christian Wiencke, Armin Stingl
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Publication number: 20160314053Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: ApplicationFiled: July 1, 2016Publication date: October 27, 2016Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Publication number: 20160231988Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.Type: ApplicationFiled: April 19, 2016Publication date: August 11, 2016Inventors: Christian Wiencke, Armin Stingl
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Patent number: 9384109Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.Type: GrantFiled: April 17, 2014Date of Patent: July 5, 2016Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
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Patent number: 9348558Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.Type: GrantFiled: August 23, 2013Date of Patent: May 24, 2016Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Christian Wiencke, Armin Stingl
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Publication number: 20160048396Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Christian WIENCKE, Armin STINGL, Jeroen VLIEGEN
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Patent number: 9203305Abstract: In a Pulse Width Modulation power converter and control method, wherein one of the operating modes steady state or load transient is detected. For either of the two operating modes one set of PID coefficients is provided for the control law that controls the duty ratio command. In case a load transient is detected, the KP gain is selected adaptively. Operating mode detection is supported by oversampling the error signal.Type: GrantFiled: November 9, 2011Date of Patent: December 1, 2015Assignee: ZENTRUM MIKROELEKTRONIK DRESDEN AGInventors: Frank Trautmann, Armin Stingl