Abstract: In some embodiments, the camera system comprises: an optical assembly to create an optical image from the optical wavefront; a deformable phase plate (DPP) to receive the optical image from the optical assembly and to adjust the optical image in accordance with a control signal, the DPP including a deformable surface suspended over a cavity filled with optical fluid, and electrical actuation elements configured to change a shape of the deformable surface based on the control signal, the electrical actuation elements arranged in a pattern in the cavity and, when activated, provide an electrostatic force on the deformable surface; an image sensor to convert the adjusted optical image into electrical signals; an image signal processor to generate a digital image from the electrical signals; and an estimator to estimate an aberration or tilt correction of the digital image and to generate the control signal based on the estimated aberration or tilt correction.

Abstract: A head-mounted device may have lenses. A user may view images through the lenses from eye boxes. The lenses may be tunable liquid lenses. Each lens may have a lens chamber. The lens chamber of the lens may have rigid and/or flexible walls that form optical lens surfaces. Actuators and/or pump and reservoir systems may deform the lens surfaces in response to control signals from a control circuit to tune the lens. Each liquid lens may have oil or other liquid in the lens chamber for that lens. Inorganic dielectric particles or other refractive-index-adjustment particles may be used to adjust the refractive index of the lens. The particles may be subwavelength in size.

Abstract: Apparatus for deflection of a beam of light includes a case, which is configured to be positioned in a path of the beam, and a liquid, which is contained within the case. An array of plates is disposed across a surface of the liquid. The plates are configured to rotate on the surface about respective axes, which are mutually parallel and are spaced apart by a predefined pitch. An actuator is configured to drive a rotation of the plates about the respective axes so as deflect the beam that is incident on the plates.

Abstract: An optical device includes first and second planar substrates having respective first and second faces and including first and second diffractive structure disposed respectively on the first and second faces. First and second planar electrodes are disposed respectively on the first and second faces. A mount holds the second planar substrate parallel to the first planar substrate, with the second face adjacent to the first face and with the first and second planar electrodes in mutual proximity, while permitting the second planar substrate to move transversely relative to the first planar substrate. A control circuit is coupled to apply an electrical potential between the first and second planar electrodes with a voltage sufficient to shift the second diffractive structure transversely relative to the first diffractive structure.

Abstract: Apparatus for deflection of a beam of light includes a case, which is configured to be positioned in a path of the beam, and a liquid, which is contained within the case. An array of plates is disposed across a surface of the liquid. The plates are configured to rotate on the surface about respective axes, which are mutually parallel and are spaced apart by a predefined pitch. An actuator is configured to drive a rotation of the plates about the respective axes so as deflect the beam that is incident on the plates.

Abstract: The invention relates to a method for producing a device with a membrane used to encapsulate a fluid contained in a cavity, in which: two substrates (110, 120) are provided; a membrane (111) is placed on one and/or on the other of the substrates; one or more walls (113) are formed, helping to laterally define the cavity (114), in which said walls are located on or in one of the substrates and/or on or in the other of the substrates, and said cavity is intended to contain the fluid, the two substrates (110, 120) are assembled together by superimposing one on the other so as to complete the cavity, in which the or each membrane (111) also helps to define the cavity, the fluid (117) is encapsulated in the cavity between the substrates, and the or each membrane is soaked by the fluid, at least a portion of one of the substrates and/or the other of the substrates is removed insofar as one and/or the other of the substrates are equipped with a membrane, in order to release the membrane at least in the central po

Abstract: The invention relates to a method for producing a device with a membrane used to encapsulate a fluid contained in a cavity, in which: two substrates (110, 120) are provided; a membrane (111) is placed on one and/or on the other of the substrates; one or more walls (113) are formed, helping to laterally define the cavity (114), in which said walls are located on or in one of the substrates and/or on or in the other of the substrates, and said cavity is intended to contain the fluid, the two substrates (110, 120) are assembled together by superimposing one on the other so as to complete the cavity, in which the or each membrane (111) also helps to define the cavity, the fluid (117) is encapsulated in the cavity between the substrates, and the or each membrane is soaked by the fluid, at least a portion of one of the substrates and/or the other of the substrates is removed insofar as one and/or the other of the substrates are equipped with a membrane, in order to release the membrane at least in the central po

Abstract: A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.

Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.

Abstract: The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract: The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract: The integrated circuit comprises at least one MOS transistor (T) including a gate (GR) having a bottom part in contact with the gate oxide. Said bottom part has an inhomogeneous work function (WFB, WFA) along the length of the gate between the source and drain regions, the value of the work function being greater at the extremities of the gate than in the centre of the gate. The gate comprises a first material (A) in the centre and a second material (B) in the remaining part. Such configuration is obtained for example by silicidation.

Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Abstract: A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor, which are arranged between a first bit line and a first storage node, and between a second bit line and a second storage node, respectively, the first access transistor and the second access transistor having a gate connected to a word line, a second plurality of transistors forming a flip-flop and situated at, at least one other level of the stack, beneath said given level, the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by means of an insulating region provided to enable coupling of said gate electrode and said channel region.

Abstract: The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET channel region of a second conductivity type which is opposite to the first conductivity type. The invention also relates to a method for fabricating such a CMOS circuit device. The fabrication of the multi-gate planar FET comprises, at an intermediate step, forming a FET channel stack with an alternating sequence of layers of a FET material and of a sacrificial material and containing main FET-channel faces, which have the same orientation as the oriented silicon surface. According to the invention, a co-integration of multi-gate FET devices is achieved that ensures high carrier mobilities for both NMOS and PMOS FETs.

Abstract: The invention concerns a method of forming a silicon germanium conduction channel under a gate stack (6) of a semiconductor device, the gate stack being formed on a silicon layer (4) on an insulating layer (2), the method comprising: growing a silicon germanium layer (14) over said silicon layer; and heating the device such that germanium condenses in said silicon layer (4) such that a silicon germanium channel (18) is formed between said gate stack and said insulating layer.