Patents by Inventor Arnaud Turier

Arnaud Turier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8179708
    Abstract: A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selected bit-line is read such that parasitic capacitance effects on the selected bit-line are reduced.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: May 15, 2012
    Assignee: Atmel Corporation
    Inventors: Arnaud Turier, Lotfi B. Ammar
  • Patent number: 8004924
    Abstract: A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: August 23, 2011
    Assignee: Atmel Corporation
    Inventors: Sylvain Leomant, Jimmy Fort, Arnaud Turier, Laurent Vachez, Lotfi B. Ammar
  • Publication number: 20100208539
    Abstract: A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 19, 2010
    Applicant: Atmel Corporation
    Inventors: Sylvain Leomant, Jimmy Fort, Arnaud Turier, Laurent Vachez, Lotfi Ben Ammar
  • Publication number: 20100208505
    Abstract: A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selected bit-line is read such that parasitic capacitance effects on the selected bit-line are reduced.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 19, 2010
    Applicant: Atmel Corporation
    Inventors: Arnaud Turier, Lotfi B. Ammar
  • Patent number: 7684244
    Abstract: A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: March 23, 2010
    Assignee: Atmel Corporation
    Inventors: Salwa Bouzekri Alami, Arnaud Turier, Lotfi Ben Ammar
  • Publication number: 20080285326
    Abstract: A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 20, 2008
    Applicant: Atmel Corporation
    Inventors: Salwa Bouzekri Alami, Arnaud Turier, Lotfi Ben Ammar