Patents by Inventor Arnd Scholz
Arnd Scholz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8138538Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.Type: GrantFiled: October 10, 2008Date of Patent: March 20, 2012Assignee: Qimonda AGInventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
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Patent number: 7867912Abstract: A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.Type: GrantFiled: February 20, 2007Date of Patent: January 11, 2011Assignee: Qimonda AGInventors: Dirk Caspary, Arnd Scholz, Stefano Parascandola, Christoph Nölscher
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Patent number: 7863136Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.Type: GrantFiled: September 30, 2008Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Matthias Goldbach, Jessica Hartwich, Lars Dreeskornfeld, Arnd Scholz, Tobias Mono
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Publication number: 20100090264Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.Type: ApplicationFiled: October 10, 2008Publication date: April 15, 2010Applicant: Qimonda AGInventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
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Publication number: 20100078711Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: Qimonda AGInventors: Matthias Goldbach, Jessica Hartwich, Lars Dreeskornfeld, Arnd Scholz, Tobias Mono
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Publication number: 20090321805Abstract: One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicant: Qimonda AGInventors: Johannes von Kluge, Arnd Scholz, Joerg Radecker, Matthias Patz, Stephan Kudelka, Alejandro Avellan
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Patent number: 7622354Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.Type: GrantFiled: August 31, 2007Date of Patent: November 24, 2009Assignee: Qimonda AGInventors: Lars Dreeskornfeld, Jessica Hartwich, Tobias Mono, Arnd Scholz, Stefan Slesazeck
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Publication number: 20090057778Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.Type: ApplicationFiled: August 31, 2007Publication date: March 5, 2009Inventors: Lars Dreeskornfeld, Jessica Hartwich, Tobias Mono, Arnd Scholz, Stefan Slesazeck
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Publication number: 20080299722Abstract: The present invention provides a method for forming a recessed channel transistor comprising the steps of: forming a plurality of active areas lines in a semiconductor substrate with an upper surface, said lines being segmented by segmentation structures having an upper surface height differing from the substrate surface; forming a first and a second extension region arranged above the active area and adjacent said segmentation structures; forming recessed channel devices in the active area segments in the remaining portion of the active area segment between said extension regions.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Inventors: Jessica Hartwich, Andrew Graham, Arnd Scholz, Yimin Wang, Stefan Slesazeck, Lars Heineck, Franz Hofmann
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Publication number: 20080296674Abstract: A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicant: QIMONDA AGInventors: Andrew Graham, Jessica Hartwich, Arnd Scholz
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Publication number: 20080283910Abstract: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.Type: ApplicationFiled: May 15, 2007Publication date: November 20, 2008Applicant: QIMONDA AGInventors: Lars Dreeskornfeld, Dongping Wu, Jessica Hartwich, Juergen Holz, Arnd Scholz
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Publication number: 20080197394Abstract: A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Applicant: QIMONDA AGInventors: Dirk Caspary, Arnd Scholz, Stefano Parascandola, Christoph Noelscher
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Publication number: 20070176253Abstract: A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.Type: ApplicationFiled: January 31, 2006Publication date: August 2, 2007Inventors: Peng-Fei Wang, Rolf Weis, Joachim Nuetzel, Arnd Scholz, Alexander Sieck, Sigurd Zehner
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Publication number: 20060134877Abstract: A buried conductive connection to a trench capacitor is formed in such a way that a contact area is provided between a conductive material layer which is arranged in the trench of the trench capacitor and contains a dopant and a semiconductor substrate between a first and a second predetermined trench depth, then dopant is outdiffused into the semiconductor substrate via the contact area by means of heating, in order to form the buried conductive connection in the semiconductor substrate, and afterward the conductive material layer containing the dopant is etched back into the trench as far as a third trench depth lying between the first and second predetermined trench depths, and the trench is covered with an insulation layer.Type: ApplicationFiled: November 23, 2005Publication date: June 22, 2006Applicant: INFINEON TECHNOLOGIES AGInventors: Bernd Goebel, Dietmar Temmler, Arnd Scholz
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Patent number: 6951822Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes etching a stud from a semiconductor material including a first spacer positioned on the sidewalls of the deep trench, wherein two of the sidewalls are formed of isolation trench oxide. The method further includes depositing an oxide layer on the surface of the semiconductor, and depositing a second spacer in the deep trench of the semiconductor, wherein the second spacer has a positive taper relative to the isolation trench oxide.Type: GrantFiled: September 28, 2001Date of Patent: October 4, 2005Assignee: Infineon Technologies North America Corp.Inventor: Arnd Scholz
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Patent number: 6620699Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.Type: GrantFiled: September 28, 2001Date of Patent: September 16, 2003Assignee: Infineon Technologies North America Corp.Inventors: Arnd Scholz, Prakash C. Dev
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Publication number: 20030062557Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Arnd Scholz, Prakash C. Dev
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Publication number: 20030064589Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes etching a stud from a semiconductor material including a first spacer positioned on the sidewalls of the deep trench, wherein two of the sidewalls are formed of isolation trench oxide. The method further includes depositing an oxide layer on the surface of the semiconductor, and depositing a second spacer in the deep trench of the semiconductor, wherein the second spacer has a positive taper relative to the isolation trench oxide.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Arnd Scholz