Abstract: An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.

Abstract: An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.

Abstract: Methods for fabricating a semiconductor structure is provided wherein the diffusion region includes at least two regions of different depth, the deepest of which is aligned to the trench isolation region of the structure. Semiconductor structures such as FETs, resistors, bipolar transistors, capacitors and diodes comprising a semiconductor substrate having a surface; an external device region on the surface of said semiconductor substrate; a channel region of a first dopant type in said semiconductor substrate under said FET; and a doped region of a second dopant type in said substrate, said doped region comprising a first portion abutting said channel region, of a first depth, and a second portion abutting said first portion, of a second depth which is deeper than the depth of the first portion is also provided.

Abstract: A method of substantially reducing stress in a trench comprising forming at least one trench in a substrate, said substrate having a surface; filling the at least one trench with a trench dielectric material; planarizing the filled trench stopping on said surface of said substrate; and subjecting the planarized trench to an anneal step, said anneal step being carried out under rapid thermal conditions at a temperature of about 800° C. or above and in the presence of an atmosphere comprising hydrogen.