Patents by Inventor Arnel Senosa Trasporto

Arnel Senosa Trasporto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8658470
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; attaching an integrated circuit device on the die paddle, the trench between the integrated circuit device and the perimeter; attaching an electrical connector to the integrated circuit device and to the upper portion; and applying an encapsulation over the integrated circuit device, the electrical connector, the die paddle, and the interconnect, the concave indentation exposed below the encapsulation.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: February 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8633063
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8629567
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20140011315
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Publication number: 20140008774
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a lead-frame having an inner portion and a bottom cover directly on a bottom surface of the inner portion; forming an insulation cover directly on the lead-frame with the insulation cover having a connection opening; connecting an integrated circuit die to the lead-frame through the connection opening with the integrated circuit die over the insulation cover; forming a top encapsulation directly on the insulation cover; forming a routing layer having a conductive land directly on the bottom cover by shaping the lead-frame; and forming a bottom encapsulation directly on the conductive land with the bottom cover exposed from the bottom encapsulation.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8623708
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a lead-frame having an inner portion and a bottom cover directly on a bottom surface of the inner portion; forming an insulation cover directly on the lead-frame with the insulation cover having a connection opening; connecting an integrated circuit die to the lead-frame through the connection opening with the integrated circuit die over the insulation cover; forming a top encapsulation directly on the insulation cover; forming a routing layer having a conductive land directly on the bottom cover by shaping the lead-frame; and forming a bottom encapsulation directly on the conductive land with the bottom cover exposed from the bottom encapsulation.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8623711
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8592252
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: November 26, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 8569112
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 29, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8557638
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130256861
    Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.
    Type: Application
    Filed: March 8, 2013
    Publication date: October 3, 2013
    Applicant: STATS CHIPPAC LTD.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130249118
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130249068
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130249065
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130249077
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8525325
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 3, 2013
    Assignee: Stats ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8519518
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 27, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Reza Argenty Pagaila, Linda Pei Ee Chua, Arnel Senosa Trasporto
  • Patent number: 8513788
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: August 20, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154072
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154118
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua