Abstract: Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.

Abstract: Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.

Abstract: A detection method for identifying unintentionally forward-biased diode devices identifies one or more forward-biased diodes directly from a graphical representation of an integrated circuit (IC) device design. The graphical representation describing one or more IC components as a plurality of geometric shapes that correspond to a set of patterns in at least one semiconductor layer. A detection method may work in conjunction with one or more checks (e.g., electrical rule check (ERC)) to analyze the graphical representation and ensure its manufacturability by reducing the likelihood the forward-biased diodes will be present in the manufactured IC device.

Abstract: A detection method for identifying unintentionally forward-biased diode devices identifies one or more forward-biased diodes directly from a graphical representation of an integrated circuit (IC) device design. The graphical representation describing one or more IC components as a plurality of geometric shapes that correspond to a set of patterns in at least one semiconductor layer. A detection method may work in conjunction with one or more checks (e.g., electrical rule check (ERC)) to analyze the graphical representation and ensure its manufacturability by reducing the likelihood the forward-biased diodes will be present in the manufactured IC device.

Abstract: A power clamp in a triple well is disclosed. A metal oxide semiconductor (MOS) varactor is used in a triggering circuit and is positioned in a first N type well. An N-channel field effect transistor is positioned in a P-type well. A P-channel field effect transistor is positioned in a second N-type well. The first N-type well is electrically isolated from the second N-type well, and electrically contacts the substrate of the power clamp.

Abstract: A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.

Abstract: A circuit for detecting delay of more than a set period of time from a last signal transition for any of a plurality of data signals, comprising a differential comparator, and integrator pairs for each signal, one integrator of the pair being triggered by transition of the signal from low to high and the other triggered by transition of the inverse of the signal from low to high, each integrator having a voltage measured by the differential comparator against a reference voltage, each integrator being reset by the trigger for the other integrator.