Abstract: The present invention is a circuit for regulating the current across an impedance load. This current regulating circuit is comprised of a main current path including a first control path, a reference-current path including a similar, second control path, and a control means including a pulse generator, a current source controller and an operational amplifier for controlling the first and second control paths in parallel.

Abstract: A two-way data transfer device for the data interface between two data-exchanging cells including a data source and a data sink with at least one buffer provided in each cell. When the transmitter buffer is full or the receiver buffer is empty, a backward cell stop signal freezes the state of the data source or the data sink and the cell stop signals are controlled by status signals from the respective buffers.

Abstract: An integrated CMOS multiplication circuit is operated in a parallel-serial mode and executes binary multiplication of a multiplicand and multiplier within the period of a system clock signal by an improved implementation of the two's complement method. The multiplication circuit includes an input shift register for receiving the multiplicand bits in parallel and reading them out serially as clocked by an internal clock signal of higher frequency than the system clock signal, a single chain of multiplying stages each receiving a respective one of the multiplier bits and the serially read-out multiplicand bits and performing successive partial product operations thereon, a parallel adder having a corresponding number of adding stages for successively adding the sum and carry bit outputs of the multiplying stages, an output shift register for serially receiving the output bits of the parallel adder, and a clock driver which generates the higher frequency internal clock signal from the system clock signal.

Abstract: A CMOS/NMOS integrated circuit realizes individual logic circuits with a combination of CMOS and enhancement-mode NMOS devices. The parameters of the CMOS and NMOS devices are selected such that the supply voltage dependency of the CMOS devices is offset by the supply voltage dependency of the NMOS devices. Thus, the propagation delays in the CMOS and NMOS devices, individually a function of supply voltage, remain constant for variations in the supply voltage. The logic circuits include analog-to-digital converters, adders, multipliers, flip flops and ring oscillators. The ring oscillator includes two blocks of inverters. The first block comprises CMOS inverters connected in series; the second block comprises enhancement-mode NMOS inverters connected in series. The output of the first block is connected to the input of the second block, and the output of the second block is connected to the input of the first block, thus forming a "ring" of inverters.

Abstract: A monolithic integrated digital circuit including at least one circuit for the serial data processing of multi-digit data signals synchronized to a clock system, the serial data processing circuits using a clock signal coming from a clock oscillator which is also integrated. The clock oscillator includes an odd number of ring-connected inverting stages. The output of the oscillator is provided to a counter. When the counter counts a number of pulses equal to the number of digits of the output signal of the data processing circuit, the counter stops the clock oscillator. The system clock signal is applied to both the reset input of the counter and the synchronizing input of the data processing circuit.

Abstract: A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS inverter employing a P-intermediate transistor between both the P- and the N-transistor. The gates of the intermediate transistors are interconnected and controlled by the clock signal, whereas the inverter input is constituted by the interconnected gates of the P- and the N-transistor of each inverter. Such an inverter chain can be used, for example, as a digital pulse width discriminator, as a final position counter, as a circuit for compensating signal drop-outs in input pulses, or else for effecting ring oscillator synchronizations.

Abstract: To implement CMOS EXORs or EXNORs, four transistors are used which have one end of their channels tied to the gate output. The first and fourth transistors are one conductivity type, and the second and third transistors are of the other conductivity type. One of the inputs is split up into two sub-inputs to which one of the digital signals has to be applied in uninverted form and in inverted form, respectively. The other end of the channel of the fourth transistor is connected to the first sub-input in the case of the EXOR and to the second sub-input in the case of the EXNOR. The reverse is true for the channel of the third transistor, while the channels of the first and second transistors are connected to the second input. The latter is also connected to the gates of the third and fourth transistors. The gate of the first transistor is connected to the channel of the fourth transistor, while the gate of the second transistor is connected to the channel of the third transistor.

Abstract: To increase the computing speed when forming the product of a first binary number (x) and a second binary number (y) and then adding (xy+z) a third binary number (z) by means of a multiplier (mw) and an adder (aw), the individual full-adder stages of the adder (aw) except the stage for the sign digit are inserted as an additional row between the next to the last row and the output row of the multiplier, the full-adder for the sign digit of the output row (az) being also omitted. The two omitted stages are replaced with a sign-correcting stage (vk).

Abstract: A fast and inexpensive MOS switched carry parallel full adder is disclosed. Each stage includes only one inverter and two shunting transistors for the carry signal, one transistor being of the depletion type. Each stage further includes two EXCLUSIVE-OR gates and two NOR gates.

Abstract: The ternary-binary conversion is reached by two CMOS inverters dimensioned extremely unsymmetrically with regard to their W/L ratio and connected in parallel at their inputs. By further addition of a NAND or a NOR gate the circuit can be used in an integrated circuit as option releasing stage without additional terminal for the option signal which has only to be chosen as the middle value of the ternary signal whereas its lower and upper values are the binary signals.