Abstract: A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.

Abstract: A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Abstract: A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.

Abstract: A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Abstract: Provided are mechanisms for improving bandwidth for non-essential data on deterministic aircraft data networks (ADNs) such as ARINC 664 networks. A switch such as an ARINC 664 switch maintains rate constrains on one or more priority levels of traffic while releasing rate constraints on low priority traffic. Low priority traffic can be received at an ARINC 664 switch at rates allowed by an Ethernet physical layer. However, low priority, non-rate constrained traffic is transmitted only when there are no other scheduled messages to send. Low priority traffic can consume all available bandwidth whenever there is slack time. A switch can further be separated into zones including a standard rate constrained zone as well as a rate unconstrained zone. Internal or external cross-links can be provided between the zones for any data that needs to be transferred between zones.

Abstract: Provided are mechanisms for improving bandwidth for non-essential data on deterministic aircraft data networks (ADNs) such as ARINC 664 networks. A switch such as an ARINC 664 switch maintains rate constrains on one or more priority levels of traffic while releasing rate constraints on low priority traffic. Low priority traffic can be received at an ARINC 664 switch at rates allowed by an Ethernet physical layer. However, low priority, non-rate constrained traffic is transmitted only when there are no other scheduled messages to send. Low priority traffic can consume all available bandwidth whenever there is slack time. A switch can further be separated into zones including a standard rate constrained zone as well as a rate unconstrained zone. Internal or external cross-links can be provided between the zones for any data that needs to be transferred between zones.

Abstract: A system for determining a worst case latency for a specific information flow that is part of a plurality of information flows and a worst case backlog for a specific queue that is part of a plurality of queues is disclosed. The plurality of information flows and plurality of queues are part of a configuration. The system performs operations including determining a maximum busy period length for the configuration. The operations include determining a set of candidate starting times for the configuration based on the maximum busy period length. The operations further include determining a maximum layout for a plurality of information flows within the configuration. The operations include updating the worst case latency and the worst case backlog based on the maximum layout. Finally, the operations include determining the worst case latency for the specific information flow and the worst case backlog for a specific queue.

Abstract: A system for determining a worst case latency for a specific information flow that is part of a plurality of information flows and a worst case backlog for a specific queue that is part of a plurality of queues is disclosed. The plurality of information flows and plurality of queues are part of a configuration. The system performs operations including determining a maximum busy period length for the configuration. The operations include determining a set of candidate starting times for the configuration based on the maximum busy period length. The operations further include determining a maximum layout for a plurality of information flows within the configuration. The operations include updating the worst case latency and the worst case backlog based on the maximum layout. Finally, the operations include determining the worst case latency for the specific information flow and the worst case backlog for a specific queue.

Abstract: A plurality of modular equipment centers (MECs) spatially distributed throughout a vehicle servicing equipment loads. Each MEC independently provides localized power and communication to service the equipment loads and each equipment load is serviced by the nearest MEC. In at least one embodiment, only primary power is distributed across section breaks of the vehicle to minimize the number of connections between section breaks, reduce overall vehicle weight, and to increase vehicle build rate.

Abstract: A plurality of modular equipment centers (MECs) spatially distributed throughout a vehicle servicing equipment loads. Each MEC independently provides localized power and communication to service the equipment loads and each equipment load is serviced by the nearest MEC. In at least one embodiment, only primary power is distributed across section breaks of the vehicle to minimize the number of connections between section breaks, reduce overall vehicle weight, and to increase vehicle build rate.

Abstract: Bus interface units (BIUs)(54) perform fault detection, identification, and reconfiguration for all information transfers between redundant central processing units (CPUs)(56) and memory or input/output (I/O)(57A-C) in a mesh interconnected array of a highly reliable fault-tolerant computer system. Errors are detected by self-checking within the BIUs, signal parity checks by the BIUs, cross channel comparisons, and mesh transaction assessments. Fault identification and mesh reconfiguration for the mesh is performed such that no faulty unit remains active in decision making after reconfiguration, and the number of good units isolated during reconfiguration is minimized.