Abstract: A packaging structure including at least one hermetically sealed cavity in which at least one microelectronic device is arranged, the cavity being formed between a substrate and at least one cap layer through which several release holes are formed. Several separated portions of metallic material are provided such that each of the separated portions of metallic material is arranged on the cap layer above and around one of the release holes and forms an individual and hermetical plug of said one of the release holes. At least one diffusion barrier layer including at least one non-metallic material is arranged on the cap layer and forms a diffusion barrier against an atmosphere outside the cavity at least around the release holes. Parts of the diffusion barrier layer are not covered by the portions of metallic material.

Abstract: A method for packaging a microelectronic device in an hermetically sealed cavity and managing an atmosphere of the cavity with a dedicated hole, including making said cavity between a support and a cap layer such that a sacrificial material and the device are arranged in the cavity; removing the sacrificial material through at least one release hole, and hermetically sealing the release hole; making a portion of wettable material on the cap layer, around a blind hole or a part of said outside surface corresponding to a location of said dedicated hole; making a portion of fuse material on the portion of wettable material; making the dedicated hole by etching the cap layer; and reflowing the portion of fuse material with a controlled atmosphere, forming a bump of fuse material which hermetically plugs said dedicated hole.

Abstract: The present invention concerns a microelectronic package (1) comprising a microelectronic structure (2) having at least a first opening (3) and defining a first cavity (4), a capping layer (9) having at least a second opening (10) and defining a second cavity (11) which is connected to the first cavity (4), wherein the capping layer (9) is arranged over the microelectronic structure (2) such that the second opening (10) is arranged over the first opening (3), and a sealing layer (13) covering the second opening (10), thereby sealing the first cavity (4) and the second cavity (11). Moreover, the present invention concerns a method of manufacturing the microelectronic package (1).

Abstract: A packaging structure including at least one hermetically sealed cavity in which at least one microelectronic device is arranged, the cavity being formed between a substrate and at least one cap layer through which several release holes are formed; several separated portions of metallic material such that each of the separated portions of metallic material is arranged on the cap layer above and around one of the release holes and forms an individual and hermetical plug of said one of the release holes; at least one diffusion barrier layer comprising at least one non-metallic material, arranged on the cap layer and forming a diffusion barrier against an atmosphere outside the cavity at least around the release holes; and wherein parts of the diffusion barrier layer are not covered by the portions of metallic material.

Abstract: A method for packaging a microelectronic device in an hermetically sealed cavity and managing an atmosphere of the cavity with a dedicated hole, including making said cavity between a support and a cap layer such that a sacrificial material and the device are arranged in the cavity; removing the sacrificial material through at least one release hole, and hermetically sealing the release hole; making a portion of wettable material on the cap layer, around a blind hole or a part of said outside surface corresponding to a location of said dedicated hole; making a portion of fuse material on the portion of wettable material; making the dedicated hole by etching the cap layer; and reflowing the portion of fuse material with a controlled atmosphere, forming a bump of fuse material which hermetically plugs said dedicated hole.

Abstract: Method of hermetically sealing a hole with a fuse material, comprising the following steps: applying a portion of wettable material onto a surface such that it completely surrounds the hole made through said surface and is located outside the hole, or completely surrounds a first part of said surface corresponding to a location of the hole; applying a portion of fuse material on the portion of wettable material and on a second part of said surface located around the portion of wettable material; reflowing the portion of fuse material to form a bump of fuse material which has a shape corresponding to a part of a sphere, which is fastened only to the portion of wettable material and which hermetically plugs the hole; wherein the hole is made in said surface before reflowing the portion of fuse material.

Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.

Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: An integrated circuit is provided that comprises a substrate of silicon and an interconnect in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallization layer on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.

Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallisation layer (120) on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.

Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.