Patents by Inventor Aron Atkins

Aron Atkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060085176
    Abstract: A system-level description that specifies functions performed by the components and interactions thereamong is divided into a plurality of functional blocks, each corresponding to a component. At least one of the functional blocks is selectively replaced with an optimized equivalent functional block, and the functional blocks and the at least one optimized equivalent functional block are interconnected in a manner consistent with the system-level description.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 20, 2006
    Inventors: Matthew Bellantoni, William Neifert, Andrew Ladd, Matthew Grasse, Mark Kostick, Aron Atkins
  • Publication number: 20050055675
    Abstract: System and methods for generating a software object that simulates the operation of a hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the electronic device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: March 10, 2005
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins
  • Publication number: 20040122644
    Abstract: System and methods high-performance simulation of the operation of a hardware device. A software object, based on a register transfer level description of the device written in a hardware description language, such as Verilog, is used for the simulation. The invention uses global analysis techniques (i.e., analysis of the design of the electronic device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 24, 2004
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins
  • Publication number: 20040117168
    Abstract: System and methods for analyzing the design of the hardware device as a whole, rather than in fragments. This provides a basis for a high-performance simulation of the hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 17, 2004
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins
  • Publication number: 20040117167
    Abstract: System and methods for simulating a software object generated from a hardware description of an electronic device. The hardware description is a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the hardware device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).
    Type: Application
    Filed: November 7, 2003
    Publication date: June 17, 2004
    Inventors: William Neifert, Joshua Marantz, Richard Sayde, Joseph Tatham, Alan Lehotsky, Andrew Ladd, Mark Seneski, Aron Atkins