Patents by Inventor Arpit VIJAYVERGIA

Arpit VIJAYVERGIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selectively configurable charge pump
    Patent number: 11908528
    Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Arpit Vijayvergia
  • MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ
    Publication number: 20230107851
    Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 6, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Vikas RANA, Arpit VIJAYVERGIA
  • Memory circuit arrangement for accurate and secure read
    Patent number: 11551731
    Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Arpit Vijayvergia
  • CIRCUIT AND METHOD FOR ON-CHIP LEAKAGE DETECTION AND COMPENSATION FOR MEMORIES
    Publication number: 20220208279
    Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 30, 2022
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Arpit VIJAYVERGIA, Vikas RANA
  • SELECTIVELY CONFIGURABLE CHARGE PUMP
    Publication number: 20220165339
    Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 26, 2022
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Vikas RANA, Arpit VIJAYVERGIA
  • MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ
    Publication number: 20210375333
    Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
    Type: Application
    Filed: May 14, 2021
    Publication date: December 2, 2021
    Applicant: STMicroelectronics International N.V.
    Inventors: Vikas RANA, Arpit VIJAYVERGIA