Abstract: A current writing circuit for a resistive memory cell arrangement is provided. The current writing circuit comprises a first current source; a first reference potential terminal; a first switch configured to switch between the first current source and the first reference potential terminal during a write operation; a second current source; a second reference potential terminal; and a second switch configured to switch between the second reference potential terminal when the first switch is switched to the first current source, and the second current source when the first switch is switched to the first reference potential terminal, during the write operation, wherein the first current source and the second current source are of the same polarity. Further embodiments relate to a memory cell arrangement and a method of writing into a target resistive memory cell of a resistive memory cell arrangement.

Abstract: A current writing circuit for a resistive memory cell arrangement is provided. The current writing circuit comprises a first current source; a first reference potential terminal; a first switch configured to switch between the first current source and the first reference potential terminal during a write operation; a second current source; a second reference potential terminal; and a second switch configured to switch between the second reference potential terminal when the first switch is switched to the first current source, and the second current source when the first switch is switched to the first reference potential terminal, during the write operation, wherein the first current source and the second current source are of the same polarity. Further embodiments relate to a memory cell arrangement and a method of writing into a target resistive memory cell of a resistive memory cell arrangement.

Abstract: A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Abstract: An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability.

Abstract: A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the fluorinated silica glass dielectric layer comprising the following steps. A semiconductor structure having a semiconductor device structure formed therein is provided. A metal line is formed over the semiconductor structure. The metal line being electrically connected with the semiconductor device structure. An insulating layer is formed over the semiconductor structure, covering the metal line. A fluorinated silica glass dielectric layer is formed over the insulating layer. The fluorinated silica glass dielectric layer is planarized to form a planarized fluorinated silica glass dielectric layer. The planarized fluorinated silica glass dielectric layer and the insulating layer are patterned to form a via opening to the metal line, and exposing portions of the patterned fluorinated silica glass dielectric layer within the via opening.