Patents by Inventor Arthur C. Winslow
Arthur C. Winslow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8349728Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.Type: GrantFiled: November 22, 2011Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, William Hill, Kenneth E. McAvey, Jr., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
-
Patent number: 8288281Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.Type: GrantFiled: July 16, 2010Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
-
Patent number: 8242544Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.Type: GrantFiled: December 7, 2004Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
-
Publication number: 20120064718Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.Type: ApplicationFiled: November 22, 2011Publication date: March 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, William Hill, Kenneth E. McAvey, JR., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
-
Patent number: 8106513Abstract: A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper diffusion barrier layer; a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; a first capping layer on the top surface of the wire and the top surface of the dielectric layer; and a second capping layer on a top surface of the first capping layer.Type: GrantFiled: November 9, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, William Hill, Kenneth E. McAvey, Jr., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
-
Publication number: 20100279508Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.Type: ApplicationFiled: July 16, 2010Publication date: November 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
-
Patent number: 7803708Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.Type: GrantFiled: September 29, 2006Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K Stamper, Arthur C Winslow
-
Patent number: 7678683Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.Type: GrantFiled: November 1, 2006Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, William Hill, Kenneth E. McAvey, Jr., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
-
Publication number: 20100052172Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.Type: ApplicationFiled: November 9, 2009Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, William Hill, Kenneth E. McAvey, JR., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
-
Patent number: 7176119Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.Type: GrantFiled: September 20, 2004Date of Patent: February 13, 2007Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, William Hill, Kenneth F. McAvey, Jr., Thomas L. McDevitt, Anthony K. Stamper, Arthur C. Winslow, Robert Zwonik
-
Patent number: 7153776Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.Type: GrantFiled: November 6, 2003Date of Patent: December 26, 2006Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
-
Publication number: 20040099954Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.Type: ApplicationFiled: November 6, 2003Publication date: May 27, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
-
Patent number: 6528219Abstract: Photolithography tools have alignment systems for aligning a level to be printed with a level already on the wafer. Commonly a photolithography tool has several alignment systems Also, wafers may have several alignment marks, and the various alignment systems may be capable of reading several of the alignment marks. The present invention provides a method of selecting the alignment system-alignment mark combination that gives the most accurate alignment to a previous level. The inventors found that residual errors provide a metric by which to evaluate alignment system-alignment mark combinations. The combination with the least residual error is selected. Alternatively data for actual overlay measurements is compared with alignment data for each alignment system-alignment mark combination, and the combination that has the best correlation to the overlay data is selected.Type: GrantFiled: July 27, 2000Date of Patent: March 4, 2003Assignee: International Business Machines CorporationInventors: Edward W. Conrad, Paul D. Sonntag, Arthur C. Winslow
-
Patent number: 6207333Abstract: A method of fabricating an attenuating phase shift photolithographic mask which will reduce the formation of side-lobes adjacent to large structures in the kerf regions on the patterned wafer. These structures are typically much larger in size than device nominal, and this method may be applied to either one axis or both axes of the kerf structure depending on it's susceptibility to form side-lobes. A substantially defect free optical lithography mask having partially transmissive attenuating phase-shift regions, transmissive clear regions, and more opaque than partially transmissive regions is fabricated by first depositing an attenuating phase-shifting layer on the top surface of a transmissive substrate followed by deposition of a more opaque than partially transmissive layer on top of the partially transmissive attenuating phase-shifting layer. Next an image transfer layer is deposited on top of the more opaque than partially transmissive layer.Type: GrantFiled: July 29, 1999Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: William J. Adair, James J. Colelli, Erik A. Puttlitz, Timothy J. Toth, Arthur C. Winslow
-
Patent number: 5498313Abstract: In a plasma or RIE etching tool using a uniquely designed annulus around a wafer supporting pedestal, it has been found that the introduction of one or more gases in the region immediately adjacent the annulus controls the amount of etching of features in that region in the surface of the wafer mounted on the pedestal. By so controlling the amount of gas in this region, the slope of the walls of the etched features can be also controlled.Type: GrantFiled: November 3, 1993Date of Patent: March 12, 1996Assignee: International Business Machines Corp.Inventors: Michael E. Bailey, Dinh Dang, James G. Michael, Timothy E. Neary, Paul W. Pastel, Sylvia R. R. Tousley, Arthur C. Winslow