Patents by Inventor Arthur J. Beaverton

Arthur J. Beaverton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875183
    Abstract: Apparatus and method for placing data based on the content of the data in random access memory such that indexing operations are not required. A strong (e.g., cryptographic) hash is applied to a data element resulting in a signature. A weaker hash function is then applied to the signature to generate a storage location in memory for the data element. The weaker hash function assigns multiple data elements to the same storage location while the signature comprises a unique identifier for locating a particular data element at this location. In one embodiment a plurality of weak hash functions are applied successively to increase storage space utilization. In other embodiments, the assigned storage location can be determined by one or more attributes of the data element and/or the storage technology, e.g, long-lived versus short-lived data and/or different regions of the memory having different performance (e.g., access latency memory lifetime) characteristics.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: January 23, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: John Michael Czerkowicz, Arthur J. Beaverton, Steven Bagby, Sowmya Manjanatha
  • Publication number: 20150242315
    Abstract: Apparatus and method for placing data based on the content of the data in random access memory such that indexing operations are not required. A strong (e.g., cryptographic) hash is applied to a data element resulting in a signature. A weaker hash function is then applied to the signature to generate a storage location in memory for the data element. The weaker hash function assigns multiple data elements to the same storage location while the signature comprises a unique identifier for locating a particular data element at this location. In one embodiment a plurality of weak hash functions are applied successively to increase storage space utilization. In other embodiments, the assigned storage location can be determined by one or more attributes of the data element and/or the storage technology, e.g, long-lived versus short-lived data and/or different regions of the memory having different performance (e.g., access latency memory lifetime) characteristics.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: John Michael Czerkowicz, Arthur J. Beaverton, Steven Bagby, Sowmya Manjanatha
  • Patent number: 5210854
    Abstract: Firmware resident in electrically erasable programmable read only memory ("EEPROM") can be updated by a user while maintaining the intelligence of a computer system during the updating process by a control logic device. The control logic device decodes address and control signals to provide a hardware partitioning of the firmware resident in the EEPROMs to prevent writing to protected partitions of the firmware. Transfer vectors are used to provide indirect accessing of subroutines resident in the firmware. During an updating process, a new version of a subroutine is stored in a free area in the EEPROMs before the transfer vector pointing to the old version of the subroutine is updated. The window of vulnerability to errors during the updating process is minimized by only updating a page of memory containing the transfer vector that points to the old version of the subroutine after the new version has been stored.
    Type: Grant
    Filed: June 14, 1989
    Date of Patent: May 11, 1993
    Assignee: Digital Equipment Corporation
    Inventors: Arthur J. Beaverton, Thomas E. Hunt