Abstract: An integrated circuit includes a termination for a transmission line having a predetermined characteristic impedance. The termination includes a controllable impedance circuit, including a multiplier, coupled to the transmission line. A reference impedance, placed external to the integrated circuit, has an impedance related to the characteristic impedance of the transmission line.

Abstract: An integrated circuit includes a termination for a transmission line having a predetermined characteristic impedance. The termination includes a controllable impedance circuit, including a multiplier, coupled to the transmission line. A reference impedance, placed external to the integrated circuit, has an impedance related to the characteristic impedance of the transmission line.

Abstract: A high bandwidth amplifier circuit with input protection is achieved by providing a signal limiting diode circuit in the path to the positive input of the amplifier and a cross-over signal feed path for coupling a portion of the input signal from the input signal source side of the signal limiting diode circuit to the negative input of the amplifier. To maximize the overall circuit bandwidth and minimize VSWR and noise, the cross-over signal feed path is designed to couple over to the negative input of the amplifier a signal that has at a higher-end of the bandwidth range an increasing amplitude and increasingly leading phase relationship relative to the amplitude limited version of the input signal being coupled to the positive input of the amplifier. In a desirable embodiment, most of the circuitry is contained on an integrated circuit and bond wires needed for coupling serve as inductors and tune the circuitry.

Abstract: Apparatus for generating a phase startable clock signal, comprises an oscillator for providing a continuous sinusoidal input signal, a control signal source for providing a control input signal having a transition between a first state and a second state at a selected time during the signal epoch of the sinusoidal input signal, and a phase splitter, track and holds, multipliers and a summation device for operating on the sinusoidal input signal with the control input signal to produce a sinusoidal output signal commencing with a predetermined phase at a predetermined time relative to the transition.

Abstract: An all NPN transistor level-shifting differential amplifier has first and second identical amplifier halves, in which each amplifier half includes a passive voltage-shifting network coupled between a load and a current source. A main amplifier has a single-ended voltage input and an output coupled to the first node of the voltage shifting network. An output amplifier has a single-ended current output and an input coupled to the second node of the voltage shifting network. The main amplifier and output amplifiers are coupled together such that a portion of the bias and signal currents flowing through the output amplifier is reused and flows through the main amplifier, reducing bias current and power requirements. The first and second amplifier halves are coupled together with a gain-setting emitter resistor. In addition to reducing the power requirements of the amplifier, the feedback configuration of the level-shifting amplifier also increases linearity over prior art level-shifting amplifiers.

Abstract: A signal acquisition and sampling system mounted in an oscilloscope probe includes an input buffer amplifier (30) featuring shunt feedback, offset capability, input bias current compensation, and very low input capacitance. Signal sampling is accomplished by a cascaded pair of differential sampling bridges including a fast track-and-hold stage (40) followed by a slow track-and-hold stage (50). The differential configuration of the bridges features common mode rejection of strobe signal coupling into the signal path and reduces aberrations and voltage droop. The fast track-and-hold stage features Schottky diode switching bridges (42A) and (42B), low value storage capacitors (44A) and (44B), thereby resulting in a fast tracking time. The slow track-and-hold stage features low-leakage diode-connected transistor switching bridges (52A) and (52B) and a FET buffer stage, thereby resulting in fast acquisition of the fast stage output and long hold time for quantization of the sample.

Abstract: A low jitter clock phase adjust system divides an input clock signal into three clock signals having precisely equal phase differences from each other. The three clock signals are converted into current vectors and input to a trio of two-quadrature multipliers. The current vectors are multiplied by separate control signals generated from an input phase control signal. The separate control signals are generated such that only one of the separate control signals varies at a time. The result is a phase response output that is a linear function of the input phase control signal and that provides a phase adjustment range from -60.degree. to 360.degree..

Abstract: An FET buffer amplifier circuit includes two matched FET amplifiers each consisting of an FET transistor source follower biased by a source impedance. One FET transistor source follower receives an input voltage and the second FET transistor source follower is driven by the output of an operational amplifier. The positive and negative inputs of the operational amplifier are respectively coupled to the outputs of each FET transistor source follower. A negative feedback loop is created in which the output voltage of the operational amplifier is equal to the input voltage. The two FET transistors and source impedances are matched and are under substantially identical operating conditions.

Abstract: An adjustable delay element for digital systems includes a high-pass filter in parallel with a low-pass filter. The high-pass filter passes the higher frequency component of the digital signal and the low-pass filter passes the lower frequency component to introduce a delay into the digital signal. A current multiplier directs a selectable portion of the higher frequency component to aid or oppose the lower frequency component to vary the delay within the signal. An output stage receives the lower frequency component with the selected portion of the higher frequency component and reproduces the digital signal with the delay. Embodiments for both differential and single-ended versions of the corresponding delay element are disclosed.

Abstract: A trigger re-synchronization circuit providing reduced trigger gate jitter for use in a high speed display device such as an oscilloscope or digitizer. The trigger re-synchronization circuit is cascadable.

Abstract: A differential to a single-ended converter circuit includes linearizing PN junctions that compensate for input signal voltage loss in the input stage. A variable voltage source and a resistor are provided for adjusting the voltage produced across these junctions by varying the current through these junctions. The converter circuit also includes a shunt feedback amplifier for inverting half the differential output voltage so that it sums with the differential voltage of opposite phase to produce the single-ended output signal. The shunt feedback amplifier is operated at a constant current to minimize error voltages. Bootstrapping is employed to linearize thermal distortion of the PN junctions and means are provided for compensating for the resulting thermal distortion.

Abstract: A differential transconductance amplifier includes two error amplifiers which provide an error correction current which linearizes a main differential amplifier. Two reference transistors coupled to the main differential amplifier provides two sets of input voltages to the two error correction amplifiers. The output currents of the main amplifier and the two error correction amplifiers are summed to produce a linearized output.

Abstract: A precision current generator provides an output current responsive to a reference supply voltage. The current generator comprises a voltage generator which drives the input to a buffer amplifier. The buffer amplifier output drives the bases of multiple output transistors, the collectors of which form the current outputs. The output current is not dependent upon transistor beta, junction voltage, temperature or supply voltage. The all NPN design enables the current generator to track the reference voltage at high frequencies without peaking or ringing of the output current and without voltage coupling between output devices.

Abstract: A variable transient response control for linear integrated-circuit high-frequency amplifiers comprises a variable equivalent resistive damping network interposed in the signal transmission path, and an electronic control circuit therefor. The resistive network includes preferably Schottky diodes having low inductance and a determinable equivalent resistance in the forward conducting condition.

Abstract: A high-transconductance composite PNP transistor comprises a PNP transistor and three or more NPN transistors arranged in a three-terminal configuration which behaves as a PNP transistor, and yet exhibits high beta, alpha greater than one, and transconductance approaching infinity.

Abstract: A programmable sweep generator for generating a linear ramp signal of different slopes in a predetermined step sequence is disclosed. The programmable sweep generator comprises a controllable voltage generator, a voltage-to-current converter, and integrator sections. The slopes of the ramp signal may be electronically controlled by switching the controllable voltage generator, voltage-to-current converter and timing capacitors in the integrator section. The use of independent buffer amplifiers, independent control circuits, and current steering devices for each timing capacitor eliminates the need to connect a switching element in series with each timing capacitor, thereby eliminating any error or non-linearity.

Abstract: A serial DAC comprises two shift registers having their data input terminals connected together for receiving serial binary data. The shift registers are clocked alternately, whereby each shift register is clocked at substantially half the rate at which data is applied to the data input terminals of the shift registers. Two current switches are associated with the shift registers respectively, each switch being operative to steer input current to one of two output terminals if the data output of the associated shift register is a digital 1 and to steer input current to the other output terminal if the data output is a digital 0. Two current sources supply equal, constant currents to input terminals of the two current switches respectively.

Abstract: A high frequency sample and hold circuit has a sampling diode bridge for coupling an input test signal to be sampled to a holding capacitor when all of the diodes of the bridge are forward biased by an applied strobe signal, thereby charging the capacitor to the input voltage. The diode bridge substantially uncouples the input signal from the holding capacitor when the strobe current direction is reversed such that the holding capacitor retains the charge stored thereon and therefore remains charged to the current sample signal voltage at the instant the strobe current reverses direction. Any holding capacitor charging current generated by the sampling bridge as it returns to equilibrium after strobe current reversal is offset by a holding capacitor charging current of substantially equal magnitude and opposite phase generated by a compensating bridge.

Abstract: An improved bipolar analog switch comprising selectable emitter-coupled pairs of bipolar transistors in combination with an emitter follower output bipolar transistor is provided with means for matching operating characteristics of the selected emitter-coupled pair to eliminate thermal distortion and to provide precise signal replication. Also, a simplified TTL-compatible digital switch control circuit is provided.

Abstract: An oscilloscope is provided with a dual time base system in which the nonlinear startup segment of the main sweep is eliminated before delay time comparison, thereby facilitating accurate differential measurements down to and including the triggering event (zero time). System delays are built in to ensure that the displayed sweep trace also begins at the left edge of the viewing screen, and, moreover, the triggering event may be viewed on both the main and delayed sweeps. The built-in system delays may be programmable to facilitate delay matching of vertical channels or time matching of independent sweep operation.