Abstract: A method and device for correcting hardware errors without loss of resources while maintaining continuous operation of the computer system. Same method and device can be used for repair or addition of hardware parts to this system. The method and device can operate in a fault tolerant system which allows continuous service during the occurrence of a hardware failure or while parts are being repaired or added to the system. The method and device also use Hamming code to detect and correct all hardware failures, particularly a soft-soft uncorrectable error and a special uncorrectable error or a SUE.

Abstract: Fault tolerant systems allow continuous service during the occurrence of a hardware failure. To provide such service, usually dual copies of data are stored in case of a hardware failure affecting the original copy. This dual copying causes the system an overall performance degradation. The present invention discloses a device and method for performing parallel fetch and store commands, allowing multiple copying of data into storage without affecting the performance of the system. In one embodiment of the invention, a method is described utilizing a multiprocessor system having two system controllers (SCs) and a plurality of requestors defined as a plurality of central processors (CPs) and input-output (I/O) processors. Asymmetric structure is accomodated. Single and dual requests can be intermixed. Each requestor has access to both system controllers, allowing either controller to process a requestor issued command.

Abstract: A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory.

Abstract: Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any successfully-completed instructions and without any abnormal ending being provided to the program. The continued program need not have any built-in recovery or correction code. Predetermined register contents in the failed processor are stored in predetermined storage locations by the the failing processor or by a service processor (SP) when the failing processor has not been able to store this information. The predetermined contents saved from the failed processor are defined by the system architecture for saving an interruption of a program to enable the continuation of execution of the program after restoring the contents of PSWs, CRs, FPRs, GPRs, ARs, etc. if using the ESA/370 architecture.

Abstract: A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

Abstract: This is a system which is used to perform reconfiguration of storage elements in order to permit removal of one or more of the elements for servicing or other reasons. If a storage element that is to be taken off line contains material that is crucial to the continued operation of the system, that material is copied to appropriate areas in other storage elements. After all crucial material has been copied to alternate locations, the original storage element can be taken off line for servicing or other purposes.

Abstract: Method and means for validating any BSM in main storage while main storage remains available for normal system operation by all CPUs in the system. The system has plural sets of BSMs in which any set can be operationally fenced from system operation in order to validate any BSM in the fenced set, while the system normally operates with the unfenced set(s) of BSMs comprising main storage. Each BSM set has a BSM controller which is integrated with a hardware BSM tester. All cells in and the addressing circuits to any BSM can be tested by incrementing line addresses through the BSM while comparing a true pattern and then a complement pattern, and then decrementing line addresses through the BSM comparing the complement pattern and then the true pattern. The BSM testers use level sensitive scan design (LSSD) circuits in the BSM controller to serially communicate with a system service processor in response to commands from the service processor and interrupt signals from the BSM tester.