Abstract: The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by detecting, at the time of a store to memory, whether an instruction, data, or video is being updated. If the memory location that is being updated contains an instruction, the simulator takes additional steps to guarantee the correct execution of the modified instruction. If the simulator determines at the time of a store that the memory location being modified is data, the simulator needs to take no additional steps.

Abstract: The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions when translating the address of the next executable instruction resulting from a dynamic transfer of control, i.e., resulting from a return instruction. The simulator compares the address that is loaded at run time by the return instruction with the return address previously executed by that instruction. If the last return address matches, the location of the return is the same. If the last return does not match, a translate look-aside buffer is used to determine the address.

Abstract: The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application's instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction. Fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently.