Patents by Inventor Arturo M. Martinez, Jr.

Arturo M. Martinez, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making a vertical phase change memory (PCM) and a PCM device
    Patent number: 8080439
    Abstract: A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: December 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Arturo M. Martinez, Jr., Rajesh A. Rao
  • METHOD OF MAKING A VERTICAL PHASE CHANGE MEMORY (PCM) AND A PCM DEVICE
    Publication number: 20090220744
    Abstract: A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Inventors: Arturo M. Martinez, JR., Rajesh A. Rao
  • Process for forming dual metal gate structures
    Patent number: 6790719
    Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: September 14, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Eric D. Luckowski, Srikanth B. Samavedam, Arturo M. Martinez, Jr.