Abstract: An adhesive ohmic contact made to a p-type semiconductor metal substrate or layer (10) comprises tin. The contact preferably includes a tin film (24) approximately 2000 .ANG. in thickness. The p-type semiconductor compound contains mercury and, while described in conjunction with Hg.sub.1-x Cd.sub.x Te, other elements exhibiting group II and group VI chemical behavior and properties may be used. A cap layer (30) is deposited over film (24), followed by insulating layer 32. Via (34) is then formed and, to complete contact (50), a metal (36) is deposited inside via (34).

Abstract: A method for making an adhesive ohmic contact to a p-type semiconductor metal substrate or layer (10) comprises tin and lead. The contact preferably includes a tin/lead film (24) approximately 2000 .ANG. in thickness. The p-type semiconductor compound contains mercury and, while described in conjunction with Hg.sub.1-x Cd.sub.x Te, other elements exhibiting group II and group VI chemical behavior and properties may be used A cap layer (30) is deposited over film (24), followed by insulating layer (32). Via (34) is then formed and, to complete contact (50), a metal (36) is deposited inside via (34).

Abstract: The disclosure relates to oxide-semiconductor interfaces which are grown with varying amounts of fixed positive (or negative) charge. The invention utilizes these different values to form a channel stop for a charge transfer device. For HgCdTe two different oxides are used, namely, those produced by wet anodization (having large values of fixed positive charge) and plasma oxidation (having low values of fixed charge). The voltage range of operation of the active gate is determined by the difference in fixed positive charge for these regions and the insulator thicknesses.

Abstract: The disclosure relates to a system for protecting HgCdTe and the like MIS arrays from breakdown during fabrication due to electrostatic charge buildup on the array capacitors. This is accomplished by building into the structure a short circuit across the capacitor plates with a fuse region therein that will evaporate when a voltage is placed thereacross which is sufficient to cause evaporation and low enough not to damage the capacitors.

Abstract: A structure for a focal plane array substrate is disclosed that includes a focal plane array positioned above a semiconductor substrate containing a signal processor. The signal processor is connected to the image detection elements of the focal plane array by connections through the focal plane array chip itself. A method for interconnecting an image array to a signal processor located beneath the image array is also disclosed. This method includes forming holes in the imager array and forming buses connecting the imager array elements to conductors located in the holes that extend to bonding pads connected to the signal processor located below.

Abstract: The disclosure relates to a system for protecting HgCdTe and the like MIS arrays from breakdown during fabrication due to electrostatic charge buildup on the array capacitors. This is accomplished by building into the structure a short circuit across the capacitor plates with a fuse region therein that will evaporate when a voltage is placed thereacross which is sufficient to cause evaporation and low enough not to damage the capacitors.

Abstract: The disclosure relates to a method of passivating mercury cadmium telluride substrates wherein a substrate surface is lapped and cleaned and then placed in an electrolyte solution containing sulfide ions to electrolytically grow a sulfide passivating layer on the lapped and cleaned surface. A preferred electrolyte solution is formed with sodium sulfide, water and ethylene glycol.

Abstract: The disclosure relates to a stepped insulator process for HgCdTe infared focal plane devices, the insulator being a combination of two insulator materials, ZnS and SiO, which differ in dielectric constant and chemical reactivity. The structure is patterned on HgCdTe which has an accumulated surface region. The resulting configuration significantly reduces pin hole short circuits introduced during via etching and improves the operating range (channel stopping action) for a given step height over that of ZnS alone.