Patents by Inventor Arturo Yanez

Arturo Yanez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for implementing delay line circuitry
    Patent number: 7157952
    Abstract: Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 2, 2007
    Assignee: L-3 Integrated Systems Company
    Inventors: Bradley S. Avants, Arturo Yanez
  • Systems and methods for implementing delay line circuitry
    Publication number: 20060038599
    Abstract: Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.
    Type: Application
    Filed: August 20, 2004
    Publication date: February 23, 2006
    Inventors: Bradley Avants, Arturo Yanez