Abstract: A method of creating logic chains in a Boolean network of a reconfigurable fabric is provided. The method includes creating a plurality of logic chains in the reconfigurable fabric. The plurality of logic chains include at least one arithmetic logic chain and at least one non-arithmetic logic chain. A method of creating logic chains in a Boolean network of a look-up table based FPGA includes: applying a labeling method by (a) finding a depth increasing node, (b) isolating the depth increasing node, and (c) finding minimum height cuts; mapping to generate a mapping solution using the minimum height cuts; applying a duplication method to implement an exclusivity constraint; and arranging connections in the look-up table based FPGA using the logic chains.

Abstract: A reconfigurable device includes an arrangement of a plurality of cells and routing resources for transmitting signals between the cells. The plurality of cells comprises carry-select reuse cells, each of the carry-select reuse cells configured to provide for performing non-arithmetic operations using a reuse arithmetic carry chain interconnecting adjacent cells.

Abstract: One embodiment provides a computer-implemented method for processing data on a node. In this embodiment, the node first determines if a first transit buffer on the node is empty, wherein the first transit buffer is capable of holding one or more data packets destined for another node. If the first transit buffer is empty, the node transmits in a first direction a data packet stored in a first local buffer, wherein the first local buffer is capable of holding one or more data packets originating from the node. If, however, the first transit buffer is not empty, the node transmits in the first direction one or more data packets stored in the first transit buffer if a first transmission condition is satisfied. If the first transmission condition is not satisfied, the node transmits in the first direction a data packet stored in the first local buffer.

Abstract: Systems and methods for recovering and managing location information in mobile communication networks using a fast recovery protocol and load balanced query and update processes. According to the fast recovery protocol, if a location update processor does not receive a message from a global database server acknowledging receipt by the global database server of a location update message after a predetermined retry interval has elapsed since the location update message was sent by the location update processor, the location update processor sends a location update retry message after each predetermined retry interval elapses until the location update processor receives an acknowledgement message from the global database server. The global database server can use the location update retry messages and the predetermined retry interval to recover from a database or link failure. The recovery period using the fast recovery protocol is bounded by the predetermined retry interval.

Abstract: One embodiment provides a computer-implemented method for processing data on a node. In this embodiment, the node first determines if a first transit buffer on the node is empty, wherein the first transit buffer is capable of holding one or more data packets destined for another node. If the first transit buffer is empty, the node transmits in a first direction a data packet stored in a first local buffer, wherein the first local buffer is capable of holding one or more data packets originating from the node. If, however, the first transit buffer is not empty, the node transmits in the first direction one or more data packets stored in the first transit buffer if a first transmission condition is satisfied. If the first transmission condition is not satisfied, the node transmits in the first direction a data packet stored in the first local buffer.

Abstract: Systems and methods for recovering and managing location information in mobile communication networks using a fast recovery protocol and load balanced query and update processes. According to the fast recovery protocol, if a location update processor does not receive a message from a global database server acknowledging receipt by the global database server of a location update message after a predetermined retry interval has elapsed since the location update message was sent by the location update processor, the location update processor sends a location update retry message after each predetermined retry interval elapses until the location update processor receives an acknowledgement message from the global database server. The global database server can use the location update retry messages and the predetermined retry interval to recover from a database or link failure. The recovery period using the fast recovery protocol is bounded by the predetermined retry interval.

Abstract: Systems and methods for recovering and managing location information in mobile communication networks using a fast recovery protocol and load balanced query and update processes. According to the fast recovery protocol, if a location update processor does not receive a message from a global database server acknowledging receipt by the global database server of a location update message after a predetermined retry interval has elapsed since the location update message was sent by the location update processor, the location update processor sends a location update retry message after each predetermined retry interval elapses until the location update processor receives an acknowledgement message from the global database server. The global database server can use the location update retry messages and the predetermined retry interval to recover from a database or link failure. The recovery period using the fast recovery protocol is bounded by the predetermined retry interval.

Abstract: A plurality of program processors, shared memory, dual port memory, external cache memory and a control processor form a multiprocessor system. A shared memory bus links the program processors, shared memory, dual port memory and external cache memory. Program processor I/O occurs through a pair of serial I/O channels coupled to one port of the dual port memory. A write generate mode is implemented for updating cache by first allocating lines of shared memory as write before read areas. For such lines, cache tags are updated directly on cache misses without reading from memory. A hit is forced for such line, resulting in valid data at the updated part and invalid data at the remaining portion. Thus, part of the line is written to and the rest invalidated. The invalid portions are not read, unless preceded by a write operation. The mode reduces the number of bus cycles by making write misses more efficient.