Patents by Inventor Arun Kumar Nanda

Arun Kumar Nanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6500729
    Abstract: A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: December 31, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Chittipeddi, Arun Kumar Nanda, Ankineedu Velaga
  • Patent number: 6358785
    Abstract: A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: March 19, 2002
    Assignee: Lucent Technologies, Inc.
    Inventors: Sailesh Chittipeddi, Arun Kumar Nanda, Ankineedu Velaga
  • Patent number: 6325709
    Abstract: A polishing pad conditioner used in the removal of slurry and semiconductor thin film build-up in the polishing pad in a chemical and mechanical polishing (CMP) process used to planarize a semiconductor wafer surface. The conditioner is pressed against the polishing pad, often while de-ionized water is applied, to remove the material build-up. The conditioner of the present invention has a convex lower surface covered by diamond crystals that are bonded to the underside of the nickel alloy conditioner. Typically, the difference between the center and the edge of the conditioning surface will range from a minimum of about 0.2 mm (very slightly convex) to a maximum of the entire thickness of the conditioning surface (more convex). The convex shape reduces the friction between the pad and conditioner and allows the slurry to reach the center of the conditioner. This more uniformly conditions the pad surface which yields more uniformly polished wafers and also increases pad life.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: December 4, 2001
    Assignees: Chartered Semiconductor Manufacturing Ltd, Lucent Technologies, Inc.
    Inventors: Arun Kumar Nanda, Ser Wee Quek
  • Patent number: 6323126
    Abstract: A method for forming tungsten plugs and layers is disclosed. A thin layer of polysilicon or amorphous silicon is formed within a contact opening. The silicon is exposed to WF6, thereby forming a tungsten plug.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: November 27, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Chittipeddi, Arun Kumar Nanda
  • Patent number: 6110012
    Abstract: A method and apparatus for limiting or eliminating the edge effect in a chemical mechanical polishing apparatus comprising a substrate holder and a retaining ring spaced from and around the holder, a rotatable platen and a polishing pad on the platen, by essentially flattening the pad in the area in which it normally tends to deform. The invention is carried out by applying a fluid under pressure, preferably the polishing slurry, to the pad in the region of the gap between the retaining ring and the holder to substantially flatten the pad in the area around the edge of the substrate.
    Type: Grant
    Filed: December 24, 1998
    Date of Patent: August 29, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Alvaro Maury, Arun Kumar Nanda, Jose Omar Rodriguez
  • Patent number: 5686359
    Abstract: The specification describes a process for siliciding silicon metallization with titanium. The process requires two anneal steps and is based on careful control of operating parameters during the first anneal step. A prescription is given relating time and temperature of anneal, and titanium film thickness, to silicide resistivity. Proper choice of parameters also minimizes variables in the process.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: November 11, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Steven Glenn Meester, Arun Kumar Nanda, Cletus Walter Wilkins
  • Patent number: 5641994
    Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: June 24, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Cheryl Anne Bollinger, Edward Alan Dein, Sailesh Mansinh Merchant, Arun Kumar Nanda, Pradip Kumar Roy, Cletus Walter Wilkins, Jr.