Abstract: Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.

Abstract: Using metadata for a contentless file to provide a guest context access to file content. Within a guest context, a file system is mounted from a container image which lacks a first file's content and which includes metadata defining properties of the first file and mapping data defining information for identifying a second file within another filesystem from which the first file's content is obtainable Based on the properties, a filesystem operation involving the first file is performed without switching to a host context, and a requested access to the first file's content is responded to. Responding includes, based on the mapping data, communicating a request for the host context to supply the first file's content and, after returning from a context switch, responding to the requested access by supplying content of the second file from guest memory page(s) which are mapped to host memory page(s) containing the second file's content.

Abstract: Pooling computing resources based on inferences about a plurality of hardware devices. The method includes identifying inference information about the plurality of devices. The method further includes based on the inference information optimizing resource usage of the plurality of hardware devices.

Abstract: Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Abstract: Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.

Abstract: One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a hybrid binary, wherein the call is in a format for the guest architecture. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code, an interoperability thunk to handle an incompatibility between the guest architecture and the native architecture, and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk. The method further includes invoking the interoperability thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Abstract: Pooling computing resources based on inferences about a plurality of hardware devices. The method includes identifying inference information about the plurality of devices. The method further includes based on the inference information optimizing resource usage of the plurality of hardware devices.

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Abstract: Systems, methods, and apparatus for separately loading and managing foreground work and background work of an application. In some embodiments, a method is provided for use by an operating system executing on at least one computer. The operating system may identify at least one foreground component and at least one background component of an application, and may load the at least one foreground component for execution separately from the at least one background component. For example, the operating system may execute the at least one foreground component without executing the at least one background component. In some further embodiments, the operating system may use a specification associated with the application to identify at least one piece of computer executable code implementing the at least one background component.

Abstract: Pooling computing resources based on inferences about a plurality of hardware devices. The method includes identifying inference information about the plurality of devices. The method further includes based on the inference information optimizing resource usage of the plurality of hardware devices.

Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.

Abstract: One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a hybrid binary, wherein the call is in a format for the guest architecture. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code, an interoperability thunk to handle an incompatibility between the guest architecture and the native architecture, and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk. The method further includes invoking the interoperability thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

Abstract: One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a target binary, wherein the call is in a format for the guest architecture. The method further includes determining that the call is to a binary that is a hybrid binary. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code and a specialized thunk to handle an incompatibility between the guest architecture and the native architecture. The method further includes invoking the specialized thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

Abstract: Adaptive doze to hibernate scheme techniques are described for power management of a computing device. Rather than relying upon a fixed timer to control device power states, the adaptive doze to hibernate scheme monitors various hibernate parameters and adapts the hibernation experience in dependence upon the parameters. The hibernate parameters may include but are not limited to a standby budget, minimum standby time, reserve screen on time, and indications of user presence. In operation, a power manager monitors battery drain rate and adaptively determines when to change the device power states of the computing device based on the observed drain rate and the hibernate parameters. The power manager may selectively switch between various states (e.g., high performance, active, wake, standby, hibernate, off, etc.) accordingly.

Abstract: A set of memory pages from a working set of a program process, such as at least some of the memory pages that have been modified, are compressed into a compressed store prior to being written to a page file, after which the memory pages can be repurposed by a memory manager. The memory commit charge for the memory pages compressed into the compressed store is borrowed from the program process by a compressed storage manager, reducing the memory commit charge of the compressed storage manager. Subsequent requests from the memory manager for memory pages that have been compressed into a compressed store are satisfied by accessing the compressed store memory pages (including retrieving the compressed store memory pages from the page file if written to the page file), decompressing the requested memory pages, and returning the requested memory pages to the memory manager.

Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.

Abstract: Processing faults in a virtual computing environment. A method includes receiving a request to perform a memory access for a virtual machine. The method further includes identifying that that the memory access is unable to be performed without taking a fault. The method further includes identifying that a virtual fault can be taken to service the fault. The virtual fault is taken by servicing the fault asynchronously with respect to the virtual machine. The method further includes identifying that a virtual fault should be taken by evaluating criteria to weigh taking a virtual fault for servicing the fault asynchronously versus servicing the fault synchronously. As a result of identifying that a virtual fault should be taken, the method farther includes notifying the virtual machine that a virtual fault should be taken for the memory access. The method further includes servicing the fault asynchronously with respect to the virtual machine.