Patents by Inventor Arunima Dasgupta

Arunima Dasgupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Model library implementation and methodology for worst case performance modeling for SRAM cells
    Patent number: 8352895
    Abstract: Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Iread based on the local Monte Carlo simulations around process corner G, extrapolating the worst case Iread from the normal probability distribution of Iread to define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vineet Wason, Kevin J. Yang, Sriram Balasubramanian, Lingquan Wang, Varsha Balakrishnan, Juhi Bansal, Zhi-Yuan Wu, Karthik Chandrasekaran, Arunima Dasgupta
  • MODEL LIBRARY IMPLEMENTATION AND METHODOLOGY FOR WORST CASE PERFORMANCE MODELING FOR SRAM CELLS
    Publication number: 20120159419
    Abstract: Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Iread based on the local Monte Carlo simulations around process corner G, extrapolating the worst case Iread from the normal probability distribution of Iread to define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Vineet Wason, Kevin J. Yang, Sriram Balasubramanian, Lingquan Wang, Varsha Balakrishnan, Juhi Bansal, Zhi-Yuan Wu, Karthik Chandrasekaran, Arunima Dasgupta