Patents by Inventor Arup Polley

Arup Polley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160293834
    Abstract: Described examples include graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Applicant: Texas Instruments Incorporated
    Inventors: Arup Polley, Archana Venugopal, Robert Reid Doering, Luigi Colombo
  • Publication number: 20160235313
    Abstract: The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.
    Type: Application
    Filed: August 27, 2015
    Publication date: August 18, 2016
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Sharma, Sriram Narayanan, Srinath Mathur Ramaswamy, Arup Polley, Seung Bae Lee, Wen Li
  • Patent number: 9397685
    Abstract: Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input signal, an analog detector circuit to provide a detector output signal representing a feature of the input signal, a second sampling circuit to sample the detector output signal, and a control circuit to control a sample rate or other analog front end operating parameter at least partially according to the sampled detector output signal, and to selectively enable and disable the analog detector circuit at least partially according to a model representing an expected repeating waveform of the input signal.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sriram Narayanan, Srinath Mathur Ramaswamy, Arup Polley, Ajit Sharma
  • Patent number: 9319059
    Abstract: The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs?1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: April 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Sharma, Seung Bae Lee, Srinath Mathur Ramaswamy, Sriram Narayanan, Arup Polley
  • Patent number: 9148159
    Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Sharma, Seung Bae Lee, Srinath M. Ramaswamy, Sriram Narayanan, Arup Polley
  • Publication number: 20150263744
    Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Ajit Sharma, Seung Bae Lee, Srinath M. Ramaswamy, Sriram Narayanan, Arup Polley
  • Publication number: 20140368944
    Abstract: A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 18, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ARUP POLLEY, Pankaj Pandey, Bryan Bloodworth
  • Patent number: 8896950
    Abstract: A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: November 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Arup Polley, Pankaj Pandey, Bryan Bloodworth
  • Patent number: 8710904
    Abstract: Apparatus and methods disclosed herein implement a MOS resistor using the current channel of a MOS transistor. The MOS resistance R(DS) is dependent upon MOS transistor geometry and nominal gate voltage. MOS resistor terminal-to-gate voltages are averaged and applied to the MOS transistor gate such as to maintain the MOS resistor terminal voltage to current ratio, resulting in a substantially constant R(DS). R(DS) is also compensated for temperature and process variations by adjusting gate voltages via negative feedback methods.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Arup Polley
  • Publication number: 20140049314
    Abstract: Apparatus and methods disclosed herein implement a MOS resistor using the current channel of a MOS transistor. The MOS resistance R(DS) is dependent upon MOS transistor geometry and nominal gate voltage. MOS resistor terminal-to-gate voltages are averaged and applied to the MOS transistor gate such as to maintain the MOS resistor terminal voltage to current ratio, resulting in a substantially constant R(DS). R(DS) is also compensated for temperature and process variations by adjusting gate voltages via negative feedback methods.
    Type: Application
    Filed: December 27, 2012
    Publication date: February 20, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Arup Polley
  • Patent number: 8508876
    Abstract: A data storage system for detecting a location of a head relative to a magnetic media is described. This system comprises arms, a preamplifier circuit coupled to the arms for controlling the arms, a proximity sensing system positioned within the preamplifier circuit, the proximity sensing system comprising: an input stage for transmitting an input sense signal; a programmable gain stage coupled to receive the input sense signal and operative for transmitting a gain signal in response to receiving the input sense signal; a multiplexer coupled to receive the gain signal and at least one control signal, the multiplexer operative for transmitting a multiplexed signal; a detector coupled to receive the multiplexed signal and a second control signal, the detector operative for transmitting an output signal; wherein an amplitude associated with the output signal enables detecting the location of the head.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 13, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Arup Polley, Rajarshi Mukhopadhyay, Reza Sharifi, Mark A. Wolfe
  • Patent number: 8369190
    Abstract: A data storage system for detecting a location of a head relative to a magnetic media is described. This system comprises arms, a preamplifier circuit coupled to the arms for controlling the arms, a proximity sensing system positioned within the preamplifier circuit, the proximity sensing system comprising: an input stage for transmitting an input sense signal; a programmable gain stage coupled to receive the input sense signal and operative for transmitting a gain signal in response to receiving the input sense signal; a multiplexer coupled to receive the gain signal and at least one control signal, the multiplexer operative for transmitting a multiplexed signal; a detector coupled to receive the multiplexed signal and a second control signal, the detector operative for transmitting an output signal; wherein an amplitude associated with the output signal enables detecting the location of the head.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: February 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Arup Polley, Rajarshi Mukhopadhyay, Reza Sharifi, Mark A. Wolfe
  • Publication number: 20120250484
    Abstract: A data storage system for detecting a location of a head relative to a magnetic media is described. This system comprises arms, a preamplifier circuit coupled to the arms for controlling the arms, a proximity sensing system positioned within the preamplifier circuit, the proximity sensing system comprising: an input stage for transmitting an input sense signal; a programmable gain stage coupled to receive the input sense signal and operative for transmitting a gain signal in response to receiving the input sense signal; a multiplexer coupled to receive the gain signal and at least one control signal, the multiplexer operative for transmitting a multiplexed signal; a detector coupled to receive the multiplexed signal and a second control signal, the detector operative for transmitting an output signal; wherein an amplitude associated with the output signal enables detecting the location of the head.
    Type: Application
    Filed: April 4, 2011
    Publication date: October 4, 2012
    Inventors: Arup Polley, Rajarshi Mukhopadhyay, Reza Sharifi, Mark A. Wolfe