Abstract: A switched-capacitor DC-DC converter circuit may convert an input voltage into a desired output voltage level. A comparator may compare a desired voltage level to a divided version of the output voltage. A fully digital control circuit comprising a frequency divider circuit, a counter circuit, a digital control logic circuit and a gain selection circuit may generate a gain value, and a phase generator may convert the gain value into clock phase signals and control settings to control a switch array to select capacitors to produce a desired output voltage.

Abstract: Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.

Abstract: Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.

Abstract: To reduce the overall reference charge needed to perform operations, analog-to-digital converters can maintain reference voltage connections of the bit trial capacitors of the digital-to-analog converter (DAC) from the end of a current conversion to just prior to the beginning of the next acquisition phase. At the start of the next acquisition phase, the bottom plates of the bit trial capacitors of the DAC can be shorted to generate a common mode voltage. As the conversion phase begins, the bottom plates of the sampling capacitors are disconnected from the input voltage and the bottom plates of each bit trial capacitor are shorted to generate input common-mode voltage. As bit trials progress, the shorts between the bottom plates of the bit trial capacitors are removed and the bit trial results are applied to the bottom plates of the bit trial capacitors.

Abstract: A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract: Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.

Abstract: Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.