Patents by Inventor Arvind Sundararajan

Arvind Sundararajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10939143
    Abstract: The present invention relates to the field of dynamic content creation and management and more particularly to dynamically create and insert immersive promotional content in a multimedia. The multimedia requested by a user is procured from a media server (105) and the one or more objects present in the multimedia is determined. The content of the multimedia is analyzed, and a decision is taken to immerse the promotional content in the multimedia based on the analysis of the multimedia. Further, a promotional content is created in real time using the components present in the asset database (106) based on the personalized user profile. The created promotional content is overlaid and blended with a at least one object from the one or more objects in the multimedia. The created promotional content and the multimedia is joined to form a composite media and is streamed to the user device.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 2, 2021
    Assignee: Wipro Limited
    Inventors: Ganeshkumar Laxminarayanan Iyer, Arvind Sundararajan
  • Publication number: 20200314465
    Abstract: The present invention relates to the field of dynamic content creation and management and more particularly to dynamically create and insert immersive promotional content in a multimedia. The multimedia requested by a user is procured from a media server (105) and the one or more objects present in the multimedia is determined. The content of the multimedia is analyzed, and a decision is taken to immerse the promotional content in the multimedia based on the analysis of the multimedia. Further, a promotional content is created in real time using the components present in the asset database (106) based on the personalized user profile. The created promotional content is overlaid and blended with a at least one object from the one or more objects in the multimedia. The created promotional content and the multimedia is joined to form a composite media and is streamed to the user device.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Ganeshkumar Laxminarayanan Iyer, Arvind Sundararajan
  • Publication number: 20180225711
    Abstract: A system and method may be used to automatically select one of a plurality of advertisements to display on a computing device, for example, via online delivery of a gallery last-page advertisement or the like. A prior probability distribution may be obtained, and may be indicative of the relative likelihood of activation of the plurality of advertisements by a user. Bayesian statistical inference may be applied to the prior probability distribution to generate a posterior probability distribution that indicates relative likelihood of activation of the plurality of advertisements by the user, for example, with greater accuracy than the prior probability distribution. The posterior probability distribution may be used to select a first advertisement of the plurality of advertisements. A signal may be transmitted to cause the first advertisement to be displayed to the user.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Prathab Murugesan, Arvind Sundararajan, Jayesh Kapoor, Divyam Goel, Shrey Sharma
  • Patent number: 9811618
    Abstract: A method is provided for simulating a program executable by a processor and a circuit design configured to communicate with the processor. A processor on a programmable IC is configured to execute the program. Programmable resources on the programmable IC are configured to implement a plurality of interface circuits. Each of the interface circuits is configured to communicate data between the processor and a simulation environment using a respective communication protocol. The interface circuits that uses a communication protocol used by the circuit design is enabled and other ones of the interface circuits are disabled. The circuit design is simulated in a simulation environment coupled to the programmable IC. During the simulating, the program is executed on the processor and data is communicated between the processor and the computing platform using the determined one of the plurality of interface circuits.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: November 7, 2017
    Assignee: XILINX, INC.
    Inventors: Umang Parekh, Arvind Sundararajan, Sandeep Dutta
  • Patent number: 9183339
    Abstract: A circuit design is created in a computer memory in response to user input to a computer processor. The circuit design has a static portion. A virtual socket is instantiated in the circuit design in response to user input, and one or more reconfigurable modules are instantiated in the virtual socket in response to user input. The static portion of the circuit design is coupled to the one or more reconfigurable modules, and configuration data are generated from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: November 10, 2015
    Assignee: XILINX, INC.
    Inventors: Nabeel Shirazi, David Robinson, Amit Kasat, Arvind Sundararajan
  • Patent number: 8875073
    Abstract: A method relating generally to computer aided design is disclosed. In such method, a block-based model of a hardware realizable system is obtained. An internal gateway-in and an internal gateway-out of a module of the block-based model are identified. An interface protocol is assigned for the internal gateway-in and the internal gateway-out. Data type and data propagation for the module at the internal gateway-in and the internal gateway-out are analyzed. The internal gateway-in and the gateway-out are transformed into an input/output interface. Integrated code is generated for subsequent realization of the input/output interface in hardware.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Jinsong Du
  • Patent number: 8769448
    Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Nabeel Shirazi, Sean P. Caffee
  • Patent number: 8762372
    Abstract: A user can refine a search over structured data by specifying that a label or an attribute value be used to further filter the results of a query.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: June 24, 2014
    Assignee: Google Inc.
    Inventors: Bindu Reddy, Lawrence J. Brunsman, Ning Mosberger, Gaurav Ravindra Bhaya, Sarah Sirajuddin, David Kale, Jennifer L. Kozenski, Arvind Sundararajan, Puneet Agarwal
  • Publication number: 20140172550
    Abstract: A plurality of advertisements are associated with PPC (pay-per-click) payment amounts paid to third-party publishers for referrals. The PPC payment amount is based on a level of engagement for a particular user with a particular advertisement. As a result, each instance of an advertisement impression can lead to a varying PPC payment amount. The PPC payment amounts are accumulated by the publisher that successfully induces user interactions with the plurality of advertisements through a social media platform.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 19, 2014
    Applicant: MYLIKES
    Inventors: Bindu Priya REDDY, Arvind SUNDARARAJAN
  • Patent number: 8650517
    Abstract: Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: February 11, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Nabeel Shirazi, Jingzhao Ou, Chi Bun Chan
  • Patent number: 8650019
    Abstract: Approaches for creating a timed hybrid simulation model for a circuit design specification. An untimed, high-level language (HLL) data-path model is input, along with an HLL data-path interface specification that specifies input ports of the HLL data-path model. A hardware description language (HDL) control-path model that specifies port attributes and associated stitching directives is generated. Each stitching directive specifies a control port and an associated one of the input ports of the HLL data-path model. The HLL data-path and HDL control-path models are linked (314) to create the timed hybrid simulation model, and the timed hybrid simulation model is stored in a processor-readable storage medium.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: February 11, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Chi Bun Chan
  • Patent number: 8626481
    Abstract: Approaches for simulating a circuit design. A block diagram of the circuit design is displayed. Each block has at least one input and at least one output, and at least one of the input or output of each block is connected to another block. Simulation data are input to a simulation model of the circuit design. During simulation of each of a plurality of the sub-circuits with the simulation model, an output data value is determined from one or more input data values to the simulated sub-circuit. Concurrent with determining the output data value, an output tag value corresponding to the output data value is determined. Concurrent with output of the output data value from the simulated sub-circuit, each output tag value is displayed proximate an output signal line from the block corresponding to the sub-circuit.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: January 7, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Jingzhao Ou
  • Patent number: 8417965
    Abstract: An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Chi Bun Chan, Nabeel Shirazi
  • Patent number: 8219958
    Abstract: Within a system comprising a processor and a memory, a method of creating evaluation hardware within an integrated circuit can include automatically inserting, by the processor, a disable circuit block into a circuit design. The method can also include automatically selecting a location within the circuit design to insert the disable circuit block, and/or inserting an unlock circuit block into the circuit design, wherein responsive to receiving an unlock code, the unlock circuit block overrides the disable circuit block. The method also can include storing, within the memory, the circuit design comprising the disable circuit block.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: July 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Nabeel Shirazi
  • Patent number: 8042079
    Abstract: Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: October 18, 2011
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Haibing Ma, Andrew Dow, Singh Vinay Jitendra
  • Patent number: 8024678
    Abstract: An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: September 20, 2011
    Assignee: Xilinx, Inc.
    Inventors: Bradley L. Taylor, Arvind Sundararajan, Shay Ping Seng, L. James Hwang
  • Publication number: 20110225036
    Abstract: One embodiment of the present invention sets forth a technique for determining an earnings per-click for a social publisher who, along with other types of digital content, publishes advertisements within a digital content distribution channel. The earnings per-click for a social publisher is determined based on an engagement score of the publisher that indicates the effectiveness of the publisher in terms of generating successful advertising outcomes. The engagement score is computed based on the performance of the advertisements published by the social publisher as well as different metrics associated with the social publisher that are collected from the advertising platform.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 15, 2011
    Inventors: Bindu Priya REDDY, Arvind Sundararajan
  • Patent number: 8015537
    Abstract: A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: September 6, 2011
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Nabeel Shirazi
  • Publication number: 20110202517
    Abstract: A user can refine a search over structured data by specifying that a label or an attribute value be used to further filter the results of a query.
    Type: Application
    Filed: April 22, 2011
    Publication date: August 18, 2011
    Applicant: GOOGLE INC.
    Inventors: Bindu Reddy, Jonathan Brunsman, Ning Mosberger, Gaurav Ravindra Bhaya, Sarah Sirajuddin, David Kale, Jennifer L. Kozenski, Arvind Sundararajan, Puneet Agarwal
  • Patent number: 7933900
    Abstract: A user can refine a search over structured data by specifying that a label or an attribute value be used to further filter the results of a query.
    Type: Grant
    Filed: October 23, 2005
    Date of Patent: April 26, 2011
    Assignee: Google Inc.
    Inventors: Bindu Reddy, Jonathan Brunsman, Ning Mosberger, Gaurav Ravindra Bhaya, Sarah Sirajuddin, David Kale, Jennifer L. Kozenski, Arvind Sundararajan, Puneet Agarwal