Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having uniform epitaxial source or drain cut are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires. A second sub-fin structure is beneath a second stack of nanowires. A first epitaxial source or drain structure is at an end of the first stack of nanowires, the first epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall. A second epitaxial source or drain structure is at an end of the second stack of nanowires, the second epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall, the first lateral sidewall of the second epitaxial source or drain structure laterally spaced apart from the second lateral sidewall of the first epitaxial source or drain structure.

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

Abstract: Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures.

Abstract: Gate-all-around integrated circuit structures having raised wall structures for epitaxial source or drain region confinement are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface above a top surface of the first and second vertical arrangements of nanowires.

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

Abstract: A periodically-rippled patch antenna structure with metal coated trenches only along one in-plane direction or in two perpendicular in-plane directions on a dielectric substrate and ground plane and methods of fabricating the antenna radiating elements are provided. An optional layer of oxide or nitride can be placed between the substrate and metal layers as an insulation layer. This use of trenches allows for miniaturization of the patch antenna as well as dual-band degeneracy. When a square 1D rippled patch antenna is excited by a microstrip line connected along the ripples, the effective length is longer than with a line orthogonal to the ripples enabling dual mode degeneracy and antennas working at two distinct frequencies of operation.

Abstract: A method for fabricating nanoscale patterned oxide substrates and devices incorporating the substrates are provided. Highly periodic or non-periodic sinusoidal patterns and other fine oxide patterns are formed on the surface of a suitable base such as silicon. Fine oxide surface patterns are created with photolithography, etching and three different oxide formation events. Thin layers of conductor materials including graphene and metals can be applied to the oxide surface patterns of the substrate and conform to the pattern allowing morphology and physical properties the conductor layer to be tuned. Control over device characteristics is demonstrated by varying the dimensions, strain, orientation, wavelength and amplitude of graphene sheet corrugations. A patch antenna device with a periodic sinusoidal graphene sheet on a silicon oxide substrate mounted to a ground plane was demonstrated.