Abstract: Architecture for efficient processing of the evolving OTN transmission technology, standardized under ITU-T G.709, in conjunction with existing and emerging SONET/SDH protocol signals, standardized under ANSI T1.105/ITU-T G.707. The new architecture allows processing the SONET/SDH signals, and/or OTN signals, and/or SONET/SDH mapped into OTN signals more efficiently. The architecture further allows processing and multiplexing of lower order signals into a higher order signal such as quad OC-192 into OC-768 or quad OC-192 into OPU3 and OTU3. This architecture uses an embedded processor to process some of the signals' overhead in software, contributing to an additional level of flexibility in the processing. This architecture enables customization and allowing for future standard updates and upgrades. The architecture can be upgraded to SONET OC-3072, SDH STM-1024 and OTU4, which currently are not standardized. The architecture can also be used for the implementation of SONET OC-192 with OTN OTU2.

Abstract: Architecture for efficient processing of the evolving OTN transmission technology, standardized under ITU-T G.709, in conjunction with existing and emerging SONET/SDH protocol signals, standardized under ANSI T1.105/ITU-T G.707. The new architecture allows processing the SONET/SDH signals, and/or OTN signals, and/or SONET/SDH mapped into OTN signals more efficiently. The architecture further allows processing and multiplexing of lower order signals into a higher order signal such as quad OC-192 into OC-768 or quad OC-192 into OPU3 and OTU3. This architecture uses an embedded processor to process some of the signals' overhead in software, contributing to an additional level of flexibility in the processing. This architecture enables customization and allowing for future standard updates and upgrades. The architecture can be upgraded to SONET OC-3072, SDH STM-1024 and OTU4, which currently are not standardized. The architecture can also be used for the implementation of SONET OC-192 with OTN OTU2.

Abstract: A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

Abstract: A combined audio and modem interface unit includes a standard audio component and an audio/modem signal processing unit. The audio component has two internal input and two internal output channels and is selectably connectable to at least an audio left port, an audio right port and a telephone port. The signal processing unit separately processes the modem and audio signals received from the audio component. The modem and one stereo audio signal can also be modulated and sent on a single output channel.