Abstract: A flash EEPROM memory array including a cache buffer for storing lines of data being written to all addresses in main memory; a plurality of holding buffers for storing lines of data from the cache buffer addressed to a particular block of addresses in main memory; a plurality of blocks of flash EEPROM main memory for storing lines of data from a holding buffer directed to a particular block of addresses in main memory; and control circuitry for writing lines of data addressed to a particular block of addresses in main memory from the cache buffer to a holding buffer when the cache buffer fills or a holding buffer limit is reached whichever occurs first, writing valid data from an addressed block of flash memory to lines of the holding buffer not holding valid data written from the cache buffer, erasing the addressed block of flash memory, and writing all of the lines in the holding buffer to the addressed block of flash memory.