Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.

Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: A memory system and method for securing volatile memory during sleep mode using the same ECC module used to secure non-volatile memory during active mode are provided. In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode. Other embodiments are possible.

Abstract: A system and method are disclosed for an electronic integrated circuit to communicate with different hosts via different interfaces using the same host protocol. The system may use a host interface circuit to select a first set of electrical contacts or a second set of electrical contacts in order for a first host or a second host, respectively, to communicate with the electronic integrated circuit using a host protocol. The method may include switching from communicating with the first host using the first set of electrical contacts to communicating with the second host using the second set of electrical contacts in order for the second host to test the electronic integrated circuit.

Abstract: Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event.

Abstract: A system and method are disclosed for an electronic integrated circuit to communicate with different hosts via different interfaces using the same host protocol. The system may use a host interface circuit to select a first set of electrical contacts or a second set of electrical contacts in order for a first host or a second host, respectively, to communicate with the electronic integrated circuit using a host protocol. The method may include switching from communicating with the first host using the first set of electrical contacts to communicating with the second host using the second set of electrical contacts in order for the second host to test the electronic integrated circuit.

Abstract: Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event.