Abstract: The physical quantity measurement device includes a secondary flow path disposed outside a multilayer unit and configured to connect an upstream opening to a downstream opening. The secondary flow path is disposed gravitationally below a primary flow path. Ultrasonic transceivers are disposed to project into a flow in the multilayer unit. In the thus-configured physical quantity measurement device, the entry of water droplets into an ultrasonic propagation path and the adhesion of water droplets to the ultrasonic transceivers are substantially prevented, so that, even when the fluid flowing in contains water droplets, the physical quantity measurement device can measure the flow rate of the fluid and the concentration of components contained in the fluid.

Abstract: A physical quantity measurement device is provided which is capable of measuring a component in a fluid to be measured even when the fluid contains droplets such as fine water droplets. The physical quantity measurement device includes, at an inlet opening (5) of a sub-channel (7), an inflow direction regulator (13) which includes guide pieces (12) each of which is inclined at predetermined angle ? with respect to the flow direction in a main channel (1). The angle ? of inflow direction regulator (13) is set to a value that is greater than 90 degrees in relation to the flow direction of the main channel (1).

Abstract: An ultrasonic flowmeter includes: a flow path body having a flow path through which a fluid to be measured flows; a pair of ultrasonic transducers disposed in the flow path body; a substrate fixed to the flow path body; a sensor plate on which a temperature sensor for detecting a temperature of the fluid to be measured is disposed, the sensor plate being flat; and an arithmetic unit that calculates a flow rate of the fluid to be measured from a propagation time of ultrasonic waves between the pair of ultrasonic transducers and the temperature detected by the temperature sensor. The sensor plate is configured to project from the substrate and to project into a flow path cross-section of the flow path from a sensor hole provided in the flow path body at a time of fixing the substrate to the flow path body.

Abstract: A memory includes a storage element which stores the number of times of application of a rewrite voltage pulse into a memory array, and a required-time output unit which outputs data representing a required time for a rewrite operation based on the number of times of application stored in the storage element.

Abstract: In a multi-chip semiconductor device, a second semiconductor chip is stacked on a first semiconductor chip with an adhesive layer being interposed therebetween, and the first and second semiconductor chips are sealed by resin containing a mixture of, e.g., a filler. The first semiconductor chip includes a first region on a surface of which the second semiconductor chip is stacked, and a second region on a surface of which the second semiconductor chip does not stacked. In one of interconnect layers including an uppermost layer, a wiring pattern is not provided, which extends across a border between the first and second regions.

Abstract: A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.

Abstract: A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.

Abstract: A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.

Abstract: A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.