Abstract: The technology is generally directed to a coordinated power throttling mechanism for a payload using power provided by a rack such that the rack power does not exceed a threshold amount for greater than a predetermined period of time. The coordinated power throttling mechanism includes the rack providing a power throttling signal to the payload and the payload executing the power throttling upon detection of the throttling signal. The payload may detect the throttling signal and, after a delay, execute the power throttling. The delay may ensure that all payloads within the rack have detected the power throttling signal.

Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.

Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.

Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.

Abstract: A multi-stage switching fabric provides a plurality switching boxes. Each switching box includes a plurality of switches and a plurality of interconnects, and each interconnect is coupled to each switch. The switching boxes may be arranged in a first stage and a second stage. In this example, each switching box in the first stage may be coupled to each switching box in the second stage via a single high capacity cable. In this regard, each switch in the first stage may be coupled to each switch in the second stage using a reduced amount of cabling.

Abstract: Methods for configuring networks and systems including nodes and switches. In one aspect, a method includes selecting a (v, b, r, k, ?) balanced incomplete block design (BIBD), wherein the BIBD includes v elements and b blocks of k elements, each element of the v elements is in r blocks of the b blocks, and each distinct pair of elements of the v elements is in ? blocks of the b blocks. Nodes are connected to switches. Each node is assigned to a different element of the BIBD. Each switch is assigned to a different block of the BIBD. For each switch, the switch is connected to the nodes assigned to the elements included in the block assigned to the switch.

Abstract: A packet voice switch 60 and method for its operation are disclosed. The switch comprises a network switching means, preferably implemented within its host processor 78, that allows calls to be routed between a circuit-switched connection at circuit-switched interface 74 and either another circuit-switched connection at interface 74 or a packet-switched connection at packet-switched interface 76. The network switching means selects call routing for calls based on a comparison of the current quality of service for the call over the packet-switched connection vs. the extra cost of connecting the call over the circuit-switched connection. Preferably, the comparison can be adjusted for call distance, the user's own quality of service preference, and current system load. In a preferred embodiment, switch 60 communicates with a similar packet voice switch (handling the other end of the same call) in order to initiate a mid-call network switch that is transparent to the calling and called parties.

Abstract: An access server architecture, and methods for use of the architecture to increase the scalability of and balance processor load for a network access server device, are disclosed. In this architecture, packet forwarding and packet processing are distributed amongst cards serving low-speed access lines (i.e., line cards). Thus, as the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller and the high-speed ports used to access the network are largely relieved of packet processing tasks for traffic passing through the server. The egress port uses a distribution engine that performs the routing lookup for packets received at the high-speed interface, tags the packets with an adjacency table pointer, and sends them to the appropriate forwarding engine for packet processing. The route switch controller, largely uninvolved in the processing of packets, updates routing information needed by each distribution or forwarding engine.

Abstract: An access server architecture, and methods for use of the architecture, are disclosed. The architecture and methods are designed to increase the scalability of and balance processor load for a network access server device. In this architecture, packet forwarding and packet processing are distributed amongst the cards serving the low-speed access lines, such that each line card is responsible for performing forwarding and packet processing for packets associated with the low-speed ports that line card serves. As the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller, and the high-speed ports, are largely relieved of packet processing tasks because the egress port uses a distribution engine that performs a cursory examination on one or more header fields on packets received—comprehending only enough information to allow each packet to be distributed to the appropriate line card for full packet processing.

Abstract: A method and apparatus for automatic routing of multi-link circuit switched connections are shown. A routing processor monitors the behavioral characteristics of a previous connection from an originating client and stores data relating to the characteristics of the previous connection. In particular, data is stored regarding the previous connection which is not available until after call completion of the previous connection. When the originating client initiates a subsequent connection, the routing processor retrieves the data relating to the behavioral characteristics of the previous connection and efficiently routes the subsequent based upon the behavioral characteristics.

Abstract: A modem, multiple modem system, and method for operating each is disclosed. Modems in a multiple-modem system save their internal state information in a remote state memory. In the event of a modem failure, a resource controller transfers data-handling to a second available modem. The second modem configures itself using internal state information for the failed modem, as gleaned from the remote state memory. It then takes over the communication channel previously assigned to the failed modem before the modem at the opposite end of the channel discerns the modem failure and prevents call loss. This invention provides redundancy for systems that employ up to several hundred or even thousands of modems, insulating users of these systems from harmful or annoying effects due to partial equipment failure.

Abstract: A high-speed router backplane is disclosed. The disclosed construction and layout techniques enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that use signaling across the backplane at trace speeds of 2.5 Gbps or greater. Specific ranges of differential trace geometry characteristics, with significant single-ended coupling to adjacent ground planes, have been found to provide the parameters needed for such signaling. New trace routing and layering techniques also help in the realization of a backplane embodiment containing roughly 600 operable high-speed differential pairs, while also providing sufficient electromagnetic interference management to allow power distribution to occur within the same backplane.

Abstract: An access server architecture, and methods for use of the architecture, are disclosed. The architecture and methods are designed to increase the scalability of and balance processor load for a network access server. In this architecture, packet forwarding and packet processing are distributed amongst the cards serving the low-speed access lines, such that each line card is responsible for performing forwarding and packet processing for packets associated with the low-speed ports that line card serves. As the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller, and the high-speed ports, are largely relieved of packet processing tasks because the egress port uses a distribution engine that performs a cursory examination on one or more header fields on packets received—comprehending only enough information to allow each packet to be distributed to the appropriate line card for full processing.

Abstract: A packet voice switch 60 and method for its operation are disclosed. The switch comprises a network switching means, preferably implemented within its host processor 78, that allows calls to be routed between a circuit-switched connection at circuit-switched interface 74 and either another circuit-switched connection at interface 74 or a packet-switched connection at packet-switched interface 76. The network switching means selects call routing for calls based on a comparison of the current quality of service for the call over the packet-switched connection vs. the extra cost of connecting the call over the circuit-switched connection. Preferably, the comparison can be adjusted for call distance, the user's own quality of service preference, and current system load. In a preferred embodiment, switch 60 communicates with a similar packet voice switch (handling the other end of the same call) in order to initiate a mid-call network switch that is transparent to the calling and called parties.

Abstract: A method and apparatus for automatic routing of multi-link circuit switched connections are shown. A routing processor monitors the behavioral characteristics of a previous connection from an originating client and stores data relating to the characteristics of the previous connection. In particular, data is stored regarding the previous connection which is not available until after call completion of the previous connection. When the originating client initiates a subsequent connection, the routing processor retrieves the data relating to the behavioral characteristics of the previous connection and efficiently routes the subsequent based upon the behavioral characteristics.

Abstract: A high-speed router backplane is disclosed. The disclosed construction and layout techniques enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that use signaling across the backplane at trace speeds of 2.5 Gbps or greater. Specific ranges of differential trace geometry characteristics, with significant single-ended coupling to adjacent ground planes, have been found to provide the parameters needed for such signaling. New trace routing and layering techniques also help in the realization of a backplane embodiment containing roughly 600 operable high-speed differential pairs, while also providing sufficient electromagnetic interference management to allow power distribution to occur within the same backplane.

Abstract: A circuit for communicating digital data is disclosed. The circuit can connect with up to 12 digital data lines (L0 through L11) for communication under a T1 or E1 standard. Control processor 36 selects the appropriate communication standard to be used by each framer/line interface processor F0 through F11, and communicates these over control bus 38. Control processor 36 also selects an appropriate line impedance for each line input/output circuit IO0 through IO11, and communicates this information over control bus 38 to control logic 34. Control logic 34 uses control lines 39 to electronically select the impedance for each line input/output circuit IO0 through IO11. Circuit 22 can be easily configured or reconfigured to receive data with different data formats and line impedances. In one preferred embodiment, each framer/line interface processor and line input/output circuit can be independently controlled, such that multiple communication formats can be simultaneously processed by circuit 22.

Abstract: A method and apparatus for automatic routing of multi-link circuit switched connections are shown. A routing processor monitors the behavioral characteristics of a previous connection from an originating client and stores data relating to the characteristics of the previous connection. In particular, data is stored regarding the previous connection which is not available until after call completion of the previous connection. When the originating client initiates a subsequent connection, the routing processor retrieves the data relating to the behavioral characteristics of the previous connection and routes the subsequent connection along a route which is advantageous to serving the behavioral characteristics of the subsequent connection.

Abstract: A circuit and method for connecting data lines in a digital communication system are disclosed. The circuit allows either a balanced data line or an unbalanced data line to be connected to a single input port with no internal reconfiguration of the system. Connection to a balanced data line isolation transformer is provided at the port. A separate connection to ground is provided at the same port. A user connects the system to a balanced data line using a jack wired for connecting the balanced data line pair across the isolation transformer. A user connects the system to an unbalanced data line using a similar jack; however, the jack in this case is wired to short one transformer connection to the ground connection provided at the port, thereby unbalancing the transformer. In one embodiment, this second jack is part of a patch cable that accepts a coaxial connector on. one end, appropriately wired to the shorted jack on the second end.

Abstract: A circuit and method for connecting data lines to a digital communication system are disclosed. The circuit allows either a balanced data line or an unbalanced data line to be connected to a single input port with no internal reconfiguration of the system. Connection to a balanced data line isolation transformer is provided at the port. A separate connection to ground is provided at the same port. A user connects the system to a balanced data line using a jack wired for connecting the balanced data line pair across the isolation transformer. A user connects the system to an unbalanced data line using a similar jack; however, the jack in this case is wired to short one transformer connection to the ground connection provided at the port, thereby unbalancing the transformer. In one embodiment, this second jack is part of a patch cable which accepts a coaxial connector on one end, appropriately wired to the shorted jack on the second end.