Abstract: A random access memory system having at least four independent access ports. In the preferred mode, a random access memory core is accessible by two independent read ports and two independent write ports. The four ports can separately and simultaneously access the same or different addressable locations within the random access memory core, except for collision conditions. A collision condition occurs whenever more than one write ports attempt to simultaneously write into the same addressable location. Such a simultaneous write access to the same cell could produce a metastable condition wherein the data storage state is indeterminate. Collision conditions result in the aborting of at least one of the write accesses on a priority basis. The abort function also protects the hardware from short circuit.

Abstract: An improved content addressable memory includes a control circuit which, during a single clock pulse, receives and compares one search address on search address input terminals to compare addresses in N address registers, and simultaneously the control circuit conditionally writes a previously received search address into a selectable one of N address registers. With this improvement, the operating speed of the content addressable memory is increased since the writing of one search address into an address register and the searching with another search address does not require two separate clock cycles.

Abstract: A bookkeeping memory is disclosed in which a row-column matrix of storage cells are written by row and cleared by column, and output signals are generated that indicate which rows of cells are in a "0" state. Bookkeeping functions are performed extremely fast by correlating one set of items to the rows, correlating a related set of items to the columns, and performing row write/column clear/zero row detect operations in the memory.

Abstract: An improved CAM (content addressable memory) cell is provided with dual address lines operable independently for a Read operation or for a Write operation. The cell is additionally provided with dual ports so that the first port permits a data input for Write operations or alternatively a data input for Search-Compare operations. The second port (Data Output) is independently connected to enable Read out of data residing in the cell. Each CAM cell also has a coincidence line (match-hit) output to indicate when an input Search bit or word coincides with resident data within the CAM cell. The CAM cells are arranged in an array of "m" rows with each row having "n" bits to hold a "n" bit word. Operationally the array permits both "Read" and "Search-Compare" operations to be accomplished in one clock cycle rather than the usual requirement of 3-4 clock cycles.

Abstract: A time-of-day counter having a plurality of register stages for counting system clock pulses and for providing signals indicative of the status of each of the register stages is coupled by a bus to a dynamic memory of the type requiring a refresh cycle. Logic means operatively coupled to the time-of-day counter operate to pass the signals present at the output of the time-of-day registers onto the bus as memory address signals so as to effectively utilize the output signals of the time-of-day counter to periodically address all portions of the memory and to provide a refresh signal as each portion of the memory is addressed.