Patents by Inventor Ashish DHALL

Ashish DHALL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935805
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Publication number: 20230245940
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 3, 2023
    Applicant: Intel Corporation
    Inventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
  • Patent number: 11664290
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Publication number: 20210391232
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Applicant: INTEL CORPORATION
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Patent number: 11158558
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Publication number: 20210111088
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 15, 2021
    Applicant: INTEL CORPORATION
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Patent number: 10269695
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Publication number: 20170287799
    Abstract: A stiffener, an IC package and methods of fabrication of an IC package including a removable stiffener are shown. A removable stiffener for use with an integrated circuit (IC), including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Such a removable stiffener including at least one removal tab is shown. An IC package including a removable stiffener including a plurality of adhesive portions disposed between a surface of the stiffener and a surface of a substrate of the IC is shown. Methods of fabrication of an IC package including a removable stiffener are shown.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Steven A. Klein, Aditya S. Vaidya, Vijay Krishnan Subramanian, Santosh Sankarasubramanian, Pramod Malatkar, Suriyakala Suriya Ramalingam, Ashish Dhall
  • Publication number: 20170263517
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Robert F. Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Patent number: 9691675
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Publication number: 20170178988
    Abstract: A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Robert F Cheney, Ashish Dhall, Suriyakala Ramalingam
  • Publication number: 20160268213
    Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Hongjin JIANG, Robert STARKSTON, Digvijay A. RAORANE, Keith D. JONES, Ashish DHALL, Omkar G. KARHADE, Kedar DHANE, Suriyakala RAMALINGAM, Li-Sheng WENG, Robert F. CHENEY, Patrick N. STOVER