Patents by Inventor Ashish V. Naik

Ashish V. Naik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240086281
    Abstract: Methods, systems and apparatus, including computer programs encoded on computer storage medium, for predicting a likelihood of a future computer memory failure. In one aspect training data inputs are obtained, where each training data input includes correctable memory error data that describes correctable errors that occurred in a computer memory and data indicating whether the correctable errors produced a failure of the computer memory. For each training data input, image representations of the correctable memory error data included in the training data input are generated. The image representations are processed using a machine learning model to output an estimated likelihood of a future failure of the computer memory. A difference between the estimated likelihood of the future failure of the computer memory and the data indicating whether the correctable errors produced a failure of the computer memory is computed. Values of model parameters are updated using the computed difference.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Gufeng Zhang, Milad Olia Hashemi, Ashish V. Naik
  • Patent number: 11853161
    Abstract: Methods, systems and apparatus, including computer programs encoded on computer storage medium, for predicting a likelihood of a future computer memory failure. In one aspect training data inputs are obtained, where each training data input includes correctable memory error data that describes correctable errors that occurred in a computer memory and data indicating whether the correctable errors produced a failure of the computer memory. For each training data input, image representations of the correctable memory error data included in the training data input are generated. The image representations are processed using a machine learning model to output an estimated likelihood of a future failure of the computer memory. A difference between the estimated likelihood of the future failure of the computer memory and the data indicating whether the correctable errors produced a failure of the computer memory is computed. Values of model parameters are updated using the computed difference.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: December 26, 2023
    Assignee: Google LLC
    Inventors: Gufeng Zhang, Milad Olia Hashemi, Ashish V. Naik
  • Publication number: 20230342245
    Abstract: Methods, systems and apparatus, including computer programs encoded on computer storage medium, for predicting a likelihood of a future computer memory failure. In one aspect training data inputs are obtained, where each training data input includes correctable memory error data that describes correctable errors that occurred in a computer memory and data indicating whether the correctable errors produced a failure of the computer memory. For each training data input, image representations of the correctable memory error data included in the training data input are generated. The image representations are processed using a machine learning model to output an estimated likelihood of a future failure of the computer memory. A difference between the estimated likelihood of the future failure of the computer memory and the data indicating whether the correctable errors produced a failure of the computer memory is computed. Values of model parameters are updated using the computed difference.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventors: Gufeng Zhang, Milad Olia Hashemi, Ashish V. Naik
  • Patent number: 9172624
    Abstract: A patch panel device has communication ports respectively associated with a unique binary number having a number of binary digits, and a plurality of computing devices are each respectively coupled to at least one of the ports. A connectivity test includes configuring the patch panel device to send a message to a first sending device in response to receiving data at a port associated with a binary number having a first value as the respective binary digit, and not to send a message to a second sending device in response to receiving data at a port associated with a binary number having a second value as the respective binary digit. Each of the computing devices is caused to transmit data for arrival at a corresponding port, an indication is received for each device regarding whether the device received a message. A connectivity map is generated.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 27, 2015
    Assignee: Google Inc.
    Inventors: Ashish V. Naik, Amin Vahdat, Leon Poutievski